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[/] [can/] [trunk/] [bench/] [verilog/] [can_testbench_defines.v] - Diff between revs 9 and 10

Rev 9	Rev 10
Line 43...	Line 43...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2002/12/27 00:12:48 mohor`
	`// Header changed, testbench improved to send a frame (crc still missing).`
	`//`
`// Revision 1.1 2002/12/26 16:00:29 mohor`	`// Revision 1.1 2002/12/26 16:00:29 mohor`
`// Testbench define file added. Clock divider register added.`	`// Testbench define file added. Clock divider register added.`
`//`	`//`
`//`	`//`
`//`	`//`
`//`	`//`

	`// Mode register`
	`define CAN_MODE_RESET 1'h1 // Reset mode

`// Bit Timing 0 register value`	`// Bit Timing 0 register value`
`define CAN_TIMING0_BRP 6'h1 // Baud rate prescaler (2*(value+1))	`define CAN_TIMING0_BRP 6'h1 // Baud rate prescaler (2*(value+1))
`define CAN_TIMING0_SJW 2'h2 // SJW (value+1)	`define CAN_TIMING0_SJW 2'h2 // SJW (value+1)

`// Bit Timing 1 register value`	`// Bit Timing 1 register value`