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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2003/09/30 20:53:58 mohor
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// Fixing the core to be Bosch VHDL Reference compatible.
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//
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// Revision 1.8 2003/02/18 00:17:44 mohor
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// Revision 1.8 2003/02/18 00:17:44 mohor
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// Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted.
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// Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted.
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//
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//
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// Revision 1.7 2003/02/09 02:24:11 mohor
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// Revision 1.7 2003/02/09 02:24:11 mohor
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// Bosch license warning added. Error counters finished. Overload frames
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// Bosch license warning added. Error counters finished. Overload frames
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Line 84... |
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/* Mode register */
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/* Mode register */
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`define CAN_MODE_RESET 1'h1 /* Reset mode */
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`define CAN_MODE_RESET 1'h1 /* Reset mode */
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/* Bit Timing 0 register value */
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/* Bit Timing 0 register value */
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`define CAN_TIMING0_BRP 6'h0 /* Baud rate prescaler (2*(value+1)) */
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//`define CAN_TIMING0_BRP 6'h0 /* Baud rate prescaler (2*(value+1)) */
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`define CAN_TIMING0_SJW 2'h2 /* SJW (value+1) */
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//`define CAN_TIMING0_SJW 2'h2 /* SJW (value+1) */
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`define CAN_TIMING0_BRP 6'h3 /* Baud rate prescaler (2*(value+1)) */
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`define CAN_TIMING0_SJW 2'h1 /* SJW (value+1) */
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/* Bit Timing 1 register value */
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/* Bit Timing 1 register value */
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`define CAN_TIMING1_TSEG1 4'h4 /* TSEG1 segment (value+1) */
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//`define CAN_TIMING1_TSEG1 4'h4 /* TSEG1 segment (value+1) */
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`define CAN_TIMING1_TSEG2 3'h3 /* TSEG2 segment (value+1) */
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//`define CAN_TIMING1_TSEG2 3'h3 /* TSEG2 segment (value+1) */
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//`define CAN_TIMING1_SAM 1'h0 /* Triple sampling */
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`define CAN_TIMING1_TSEG1 4'hf /* TSEG1 segment (value+1) */
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`define CAN_TIMING1_TSEG2 3'h2 /* TSEG2 segment (value+1) */
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`define CAN_TIMING1_SAM 1'h0 /* Triple sampling */
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`define CAN_TIMING1_SAM 1'h0 /* Triple sampling */
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No newline at end of file
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No newline at end of file
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