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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// can_testbench_defines.v ////
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//// can_testbench_defines.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the CAN Protocal Controller ////
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//// This file is part of the CAN Protocol Controller ////
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//// http://www.opencores.org/projects/can/ ////
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//// http://www.opencores.org/projects/can/ ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// All additional information is available in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2002 Authors ////
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//// Copyright (C) 2002, 2003 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/12/26 16:00:29 mohor
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// Testbench define file added. Clock divider register added.
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//
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//
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//
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//
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//
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//
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//
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// Bit Timing 0 register value
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// Bit Timing 0 register value
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