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https://opencores.org/ocsvn/can/can/trunk
[/] [can/] [trunk/] [rtl/] [verilog/] [can_acf.v] - Diff between revs 28 and 29
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| Rev 28 |
Rev 29 |
| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2003/02/09 02:24:33 mohor
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// Bosch license warning added. Error counters finished. Overload frames
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// still need to be fixed.
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//
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// Revision 1.3 2003/01/31 01:13:37 mohor
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// Revision 1.3 2003/01/31 01:13:37 mohor
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// backup.
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// backup.
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//
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//
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// Revision 1.2 2003/01/14 12:19:35 mohor
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// Revision 1.2 2003/01/14 12:19:35 mohor
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// rx_fifo is now working.
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// rx_fifo is now working.
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| Line 89... |
Line 93... |
acceptance_mask_1,
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acceptance_mask_1,
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acceptance_mask_2,
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acceptance_mask_2,
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acceptance_mask_3,
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acceptance_mask_3,
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go_rx_crc_lim,
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go_rx_crc_lim,
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go_rx_idle,
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go_rx_inter,
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data0,
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data0,
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data1,
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data1,
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rtr1,
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rtr1,
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rtr2,
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rtr2,
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| Line 123... |
Line 127... |
input [7:0] acceptance_mask_0;
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input [7:0] acceptance_mask_0;
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input [7:0] acceptance_mask_1;
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input [7:0] acceptance_mask_1;
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input [7:0] acceptance_mask_2;
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input [7:0] acceptance_mask_2;
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input [7:0] acceptance_mask_3;
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input [7:0] acceptance_mask_3;
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input go_rx_crc_lim;
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input go_rx_crc_lim;
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input go_rx_idle;
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input go_rx_inter;
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input [7:0] data0;
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input [7:0] data0;
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input [7:0] data1;
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input [7:0] data1;
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input rtr1;
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input rtr1;
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input rtr2;
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input rtr2;
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input ide;
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input ide;
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| Line 342... |
Line 346... |
end
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end
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end
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end
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else
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else
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id_ok <=#Tp match;
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id_ok <=#Tp match;
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end
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end
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else if (reset_mode | go_rx_idle) // sample_point is already included in go_rx_idle
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else if (reset_mode | go_rx_inter) // sample_point is already included in go_rx_inter
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id_ok <=#Tp 0;
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id_ok <=#Tp 0;
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end
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end
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