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[/] [can/] [trunk/] [rtl/] [verilog/] [can_bsp.v] - Diff between revs 112 and 121
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| Rev 112 |
Rev 121 |
| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.41 2003/07/18 15:23:31 tadejm
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// Tx and rx length are limited to 8 bytes regardless to the DLC value.
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//
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// Revision 1.40 2003/07/16 15:10:17 mohor
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// Revision 1.40 2003/07/16 15:10:17 mohor
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// Fixed according to the linter.
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// Fixed according to the linter.
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//
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//
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// Revision 1.39 2003/07/16 13:12:46 mohor
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// Revision 1.39 2003/07/16 13:12:46 mohor
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// Fixed according to the linter.
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// Fixed according to the linter.
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| Line 1997... |
Line 2000... |
begin
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begin
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if (rst)
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if (rst)
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bus_free_cnt_en <= 1'b0;
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bus_free_cnt_en <= 1'b0;
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else if ((~reset_mode) & reset_mode_q | node_bus_off_q & (~reset_mode))
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else if ((~reset_mode) & reset_mode_q | node_bus_off_q & (~reset_mode))
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bus_free_cnt_en <=#Tp 1'b1;
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bus_free_cnt_en <=#Tp 1'b1;
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else if (sample_point & (bus_free_cnt==4'd10) & (~node_bus_off))
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else if (sample_point & sampled_bit & (bus_free_cnt==4'd10) & (~node_bus_off))
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bus_free_cnt_en <=#Tp 1'b0;
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bus_free_cnt_en <=#Tp 1'b0;
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end
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end
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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