| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.42 2003/08/29 07:01:14 mohor
|
|
// When detecting bus-free, signal bus_free_cnt_en was cleared to zero
|
|
// although the last sampled bit was zero instead of one.
|
|
//
|
// Revision 1.41 2003/07/18 15:23:31 tadejm
|
// Revision 1.41 2003/07/18 15:23:31 tadejm
|
// Tx and rx length are limited to 8 bytes regardless to the DLC value.
|
// Tx and rx length are limited to 8 bytes regardless to the DLC value.
|
//
|
//
|
// Revision 1.40 2003/07/16 15:10:17 mohor
|
// Revision 1.40 2003/07/16 15:10:17 mohor
|
// Fixed according to the linter.
|
// Fixed according to the linter.
|
| Line 226... |
Line 230... |
abort_tx,
|
abort_tx,
|
self_rx_request,
|
self_rx_request,
|
single_shot_transmission,
|
single_shot_transmission,
|
tx_state,
|
tx_state,
|
tx_state_q,
|
tx_state_q,
|
|
overload_request,
|
|
overload_frame,
|
|
|
/* Arbitration Lost Capture Register */
|
/* Arbitration Lost Capture Register */
|
read_arbitration_lost_capture_reg,
|
read_arbitration_lost_capture_reg,
|
|
|
/* Error Code Capture Register */
|
/* Error Code Capture Register */
|
| Line 248... |
Line 254... |
/* Clock Divider register */
|
/* Clock Divider register */
|
extended_mode,
|
extended_mode,
|
|
|
rx_idle,
|
rx_idle,
|
transmitting,
|
transmitting,
|
|
transmitter,
|
go_rx_inter,
|
go_rx_inter,
|
not_first_bit_of_inter,
|
not_first_bit_of_inter,
|
set_reset_mode,
|
set_reset_mode,
|
node_bus_off,
|
node_bus_off,
|
error_status,
|
error_status,
|
| Line 308... |
Line 315... |
tx_data_12,
|
tx_data_12,
|
/* End: Tx data registers */
|
/* End: Tx data registers */
|
|
|
/* Tx signal */
|
/* Tx signal */
|
tx,
|
tx,
|
tx_oen
|
tx_next,
|
|
tx_oen,
|
|
|
|
go_overload_frame,
|
|
go_error_frame,
|
|
go_tx,
|
|
send_ack
|
|
|
/* Bist */
|
/* Bist */
|
`ifdef CAN_BIST
|
`ifdef CAN_BIST
|
,
|
,
|
scanb_rst,
|
scanb_rst,
|
| Line 351... |
Line 364... |
input abort_tx;
|
input abort_tx;
|
input self_rx_request;
|
input self_rx_request;
|
input single_shot_transmission;
|
input single_shot_transmission;
|
output tx_state;
|
output tx_state;
|
output tx_state_q;
|
output tx_state_q;
|
|
input overload_request;
|
|
output overload_frame; // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
|
|
// be send in a row. This is not implemented, yet, because host can not send an overload request.
|
|
|
/* Arbitration Lost Capture Register */
|
/* Arbitration Lost Capture Register */
|
input read_arbitration_lost_capture_reg;
|
input read_arbitration_lost_capture_reg;
|
|
|
/* Error Code Capture Register */
|
/* Error Code Capture Register */
|
| Line 370... |
Line 386... |
/* Tx Error Counter register */
|
/* Tx Error Counter register */
|
input we_tx_err_cnt;
|
input we_tx_err_cnt;
|
|
|
output rx_idle;
|
output rx_idle;
|
output transmitting;
|
output transmitting;
|
|
output transmitter;
|
output go_rx_inter;
|
output go_rx_inter;
|
output not_first_bit_of_inter;
|
output not_first_bit_of_inter;
|
output set_reset_mode;
|
output set_reset_mode;
|
output node_bus_off;
|
output node_bus_off;
|
output error_status;
|
output error_status;
|
| Line 431... |
Line 448... |
input [7:0] tx_data_12;
|
input [7:0] tx_data_12;
|
/* End: Tx data registers */
|
/* End: Tx data registers */
|
|
|
/* Tx signal */
|
/* Tx signal */
|
output tx;
|
output tx;
|
|
output tx_next;
|
output tx_oen;
|
output tx_oen;
|
|
|
|
output go_overload_frame;
|
|
output go_error_frame;
|
|
output go_tx;
|
|
output send_ack;
|
|
|
/* Bist */
|
/* Bist */
|
`ifdef CAN_BIST
|
`ifdef CAN_BIST
|
input scanb_rst;
|
input scanb_rst;
|
input scanb_clk;
|
input scanb_clk;
|
input scanb_si;
|
input scanb_si;
|
| Line 495... |
Line 518... |
reg [2:0] error_cnt2;
|
reg [2:0] error_cnt2;
|
reg [2:0] delayed_dominant_cnt;
|
reg [2:0] delayed_dominant_cnt;
|
reg enable_overload_cnt2;
|
reg enable_overload_cnt2;
|
reg overload_frame;
|
reg overload_frame;
|
reg overload_frame_blocked;
|
reg overload_frame_blocked;
|
|
reg [1:0] overload_request_cnt;
|
reg [2:0] overload_cnt1;
|
reg [2:0] overload_cnt1;
|
reg [2:0] overload_cnt2;
|
reg [2:0] overload_cnt2;
|
reg tx;
|
reg tx;
|
reg crc_err;
|
reg crc_err;
|
|
|
| Line 541... |
Line 565... |
reg rule3_exc1_2;
|
reg rule3_exc1_2;
|
reg rule3_exc2;
|
reg rule3_exc2;
|
reg suspend;
|
reg suspend;
|
reg susp_cnt_en;
|
reg susp_cnt_en;
|
reg [2:0] susp_cnt;
|
reg [2:0] susp_cnt;
|
reg error_flag_over_blocked;
|
reg error_flag_over_latched;
|
|
|
reg [7:0] error_capture_code;
|
reg [7:0] error_capture_code;
|
reg [7:6] error_capture_code_type;
|
reg [7:6] error_capture_code_type;
|
reg error_capture_code_blocked;
|
reg error_capture_code_blocked;
|
|
|
| Line 571... |
Line 595... |
wire go_rx_crc;
|
wire go_rx_crc;
|
wire go_rx_crc_lim;
|
wire go_rx_crc_lim;
|
wire go_rx_ack;
|
wire go_rx_ack;
|
wire go_rx_ack_lim;
|
wire go_rx_ack_lim;
|
wire go_rx_eof;
|
wire go_rx_eof;
|
wire go_overload_frame;
|
|
wire go_rx_inter;
|
wire go_rx_inter;
|
wire go_error_frame;
|
|
|
|
wire last_bit_of_inter;
|
wire last_bit_of_inter;
|
|
|
wire go_crc_enable;
|
wire go_crc_enable;
|
wire rst_crc_enable;
|
wire rst_crc_enable;
|
|
|
wire bit_de_stuff_set;
|
wire bit_de_stuff_set;
|
wire bit_de_stuff_reset;
|
wire bit_de_stuff_reset;
|
|
|
wire go_early_tx;
|
wire go_early_tx;
|
wire go_tx;
|
|
|
|
wire [14:0] calculated_crc;
|
wire [14:0] calculated_crc;
|
wire [15:0] r_calculated_crc;
|
wire [15:0] r_calculated_crc;
|
wire remote_rq;
|
wire remote_rq;
|
wire [3:0] limited_data_len;
|
wire [3:0] limited_data_len;
|
| Line 597... |
Line 618... |
wire error_frame_ended;
|
wire error_frame_ended;
|
wire overload_frame_ended;
|
wire overload_frame_ended;
|
wire bit_err;
|
wire bit_err;
|
wire ack_err;
|
wire ack_err;
|
wire stuff_err;
|
wire stuff_err;
|
// of intermission, it starts reading the identifier (and transmitting its own).
|
|
wire overload_needed =1'b0;// When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
|
|
// be send in a row. This is not implemented because host can not send an overload request.
|
|
|
|
wire id_ok; // If received ID matches ID set in registers
|
wire id_ok; // If received ID matches ID set in registers
|
wire no_byte0; // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
|
wire no_byte0; // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
|
wire no_byte1; // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
|
wire no_byte1; // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
|
|
|
| Line 664... |
Line 682... |
rx_data & (bit_cnt[5:0] == ((limited_data_len<<3) - 1'b1))); // overflow works ok at max value (8<<3 = 64 = 0). 0-1 = 6'h3f
|
rx_data & (bit_cnt[5:0] == ((limited_data_len<<3) - 1'b1))); // overflow works ok at max value (8<<3 = 64 = 0). 0-1 = 6'h3f
|
assign go_rx_crc_lim = (~bit_de_stuff) & sample_point & rx_crc & (bit_cnt[3:0] == 4'd14);
|
assign go_rx_crc_lim = (~bit_de_stuff) & sample_point & rx_crc & (bit_cnt[3:0] == 4'd14);
|
assign go_rx_ack = (~bit_de_stuff) & sample_point & rx_crc_lim;
|
assign go_rx_ack = (~bit_de_stuff) & sample_point & rx_crc_lim;
|
assign go_rx_ack_lim = sample_point & rx_ack;
|
assign go_rx_ack_lim = sample_point & rx_ack;
|
assign go_rx_eof = sample_point & rx_ack_lim;
|
assign go_rx_eof = sample_point & rx_ack_lim;
|
assign go_rx_inter = ((sample_point & rx_eof & (eof_cnt == 3'd6)) | error_frame_ended | overload_frame_ended) & (~overload_needed);
|
assign go_rx_inter = ((sample_point & rx_eof & (eof_cnt == 3'd6)) | error_frame_ended | overload_frame_ended) & (~overload_request);
|
|
|
assign go_error_frame = (form_err | stuff_err | bit_err | ack_err | (crc_err & go_rx_eof));
|
assign go_error_frame = (form_err | stuff_err | bit_err | ack_err | (crc_err & go_rx_eof));
|
assign error_frame_ended = (error_cnt2 == 3'd7) & tx_point;
|
assign error_frame_ended = (error_cnt2 == 3'd7) & tx_point;
|
assign overload_frame_ended = (overload_cnt2 == 3'd7) & tx_point;
|
assign overload_frame_ended = (overload_cnt2 == 3'd7) & tx_point;
|
|
|
assign go_overload_frame = ( ((sample_point & rx_eof & (eof_cnt == 3'd6)) | error_frame_ended | overload_frame_ended) & overload_needed |
|
assign go_overload_frame = ( ((sample_point & rx_eof & (eof_cnt == 3'd6)) | error_frame_ended | overload_frame_ended) & overload_request |
|
sample_point & (~sampled_bit) & rx_inter & (bit_cnt[1:0] < 2'd2) |
|
sample_point & (~sampled_bit) & rx_inter & (bit_cnt[1:0] < 2'd2) |
|
sample_point & (~sampled_bit) & ((error_cnt2 == 3'd7) | (overload_cnt2 == 3'd7))
|
sample_point & (~sampled_bit) & ((error_cnt2 == 3'd7) | (overload_cnt2 == 3'd7))
|
)
|
)
|
& (~overload_frame_blocked)
|
& (~overload_frame_blocked)
|
;
|
;
|
| Line 706... |
Line 724... |
// Rx idle state
|
// Rx idle state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_idle <= 1'b0;
|
rx_idle <= 1'b0;
|
else if (reset_mode | go_rx_id1 | error_frame)
|
// else if (reset_mode | go_rx_id1 | error_frame)
|
|
else if (reset_mode | go_rx_id1 | go_error_frame)
|
rx_idle <=#Tp 1'b0;
|
rx_idle <=#Tp 1'b0;
|
else if (go_rx_idle)
|
else if (go_rx_idle)
|
rx_idle <=#Tp 1'b1;
|
rx_idle <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 718... |
Line 737... |
// Rx id1 state
|
// Rx id1 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_id1 <= 1'b0;
|
rx_id1 <= 1'b0;
|
else if (reset_mode | go_rx_rtr1 | error_frame)
|
// else if (reset_mode | go_rx_rtr1 | error_frame)
|
|
else if (reset_mode | go_rx_rtr1 | go_error_frame)
|
rx_id1 <=#Tp 1'b0;
|
rx_id1 <=#Tp 1'b0;
|
else if (go_rx_id1)
|
else if (go_rx_id1)
|
rx_id1 <=#Tp 1'b1;
|
rx_id1 <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 730... |
Line 750... |
// Rx rtr1 state
|
// Rx rtr1 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_rtr1 <= 1'b0;
|
rx_rtr1 <= 1'b0;
|
else if (reset_mode | go_rx_ide | error_frame)
|
// else if (reset_mode | go_rx_ide | error_frame)
|
|
else if (reset_mode | go_rx_ide | go_error_frame)
|
rx_rtr1 <=#Tp 1'b0;
|
rx_rtr1 <=#Tp 1'b0;
|
else if (go_rx_rtr1)
|
else if (go_rx_rtr1)
|
rx_rtr1 <=#Tp 1'b1;
|
rx_rtr1 <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 742... |
Line 763... |
// Rx ide state
|
// Rx ide state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_ide <= 1'b0;
|
rx_ide <= 1'b0;
|
else if (reset_mode | go_rx_r0 | go_rx_id2 | error_frame)
|
// else if (reset_mode | go_rx_r0 | go_rx_id2 | error_frame)
|
|
else if (reset_mode | go_rx_r0 | go_rx_id2 | go_error_frame)
|
rx_ide <=#Tp 1'b0;
|
rx_ide <=#Tp 1'b0;
|
else if (go_rx_ide)
|
else if (go_rx_ide)
|
rx_ide <=#Tp 1'b1;
|
rx_ide <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 754... |
Line 776... |
// Rx id2 state
|
// Rx id2 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_id2 <= 1'b0;
|
rx_id2 <= 1'b0;
|
else if (reset_mode | go_rx_rtr2 | error_frame)
|
// else if (reset_mode | go_rx_rtr2 | error_frame)
|
|
else if (reset_mode | go_rx_rtr2 | go_error_frame)
|
rx_id2 <=#Tp 1'b0;
|
rx_id2 <=#Tp 1'b0;
|
else if (go_rx_id2)
|
else if (go_rx_id2)
|
rx_id2 <=#Tp 1'b1;
|
rx_id2 <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 766... |
Line 789... |
// Rx rtr2 state
|
// Rx rtr2 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_rtr2 <= 1'b0;
|
rx_rtr2 <= 1'b0;
|
else if (reset_mode | go_rx_r1 | error_frame)
|
// else if (reset_mode | go_rx_r1 | error_frame)
|
|
else if (reset_mode | go_rx_r1 | go_error_frame)
|
rx_rtr2 <=#Tp 1'b0;
|
rx_rtr2 <=#Tp 1'b0;
|
else if (go_rx_rtr2)
|
else if (go_rx_rtr2)
|
rx_rtr2 <=#Tp 1'b1;
|
rx_rtr2 <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 778... |
Line 802... |
// Rx r0 state
|
// Rx r0 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_r1 <= 1'b0;
|
rx_r1 <= 1'b0;
|
else if (reset_mode | go_rx_r0 | error_frame)
|
// else if (reset_mode | go_rx_r0 | error_frame)
|
|
else if (reset_mode | go_rx_r0 | go_error_frame)
|
rx_r1 <=#Tp 1'b0;
|
rx_r1 <=#Tp 1'b0;
|
else if (go_rx_r1)
|
else if (go_rx_r1)
|
rx_r1 <=#Tp 1'b1;
|
rx_r1 <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 790... |
Line 815... |
// Rx r0 state
|
// Rx r0 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_r0 <= 1'b0;
|
rx_r0 <= 1'b0;
|
else if (reset_mode | go_rx_dlc | error_frame)
|
// else if (reset_mode | go_rx_dlc | error_frame)
|
|
else if (reset_mode | go_rx_dlc | go_error_frame)
|
rx_r0 <=#Tp 1'b0;
|
rx_r0 <=#Tp 1'b0;
|
else if (go_rx_r0)
|
else if (go_rx_r0)
|
rx_r0 <=#Tp 1'b1;
|
rx_r0 <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 802... |
Line 828... |
// Rx dlc state
|
// Rx dlc state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_dlc <= 1'b0;
|
rx_dlc <= 1'b0;
|
else if (reset_mode | go_rx_data | go_rx_crc | error_frame)
|
// else if (reset_mode | go_rx_data | go_rx_crc | error_frame)
|
|
else if (reset_mode | go_rx_data | go_rx_crc | go_error_frame)
|
rx_dlc <=#Tp 1'b0;
|
rx_dlc <=#Tp 1'b0;
|
else if (go_rx_dlc)
|
else if (go_rx_dlc)
|
rx_dlc <=#Tp 1'b1;
|
rx_dlc <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 814... |
Line 841... |
// Rx data state
|
// Rx data state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_data <= 1'b0;
|
rx_data <= 1'b0;
|
else if (reset_mode | go_rx_crc | error_frame)
|
// else if (reset_mode | go_rx_crc | error_frame)
|
|
else if (reset_mode | go_rx_crc | go_error_frame)
|
rx_data <=#Tp 1'b0;
|
rx_data <=#Tp 1'b0;
|
else if (go_rx_data)
|
else if (go_rx_data)
|
rx_data <=#Tp 1'b1;
|
rx_data <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 826... |
Line 854... |
// Rx crc state
|
// Rx crc state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_crc <= 1'b0;
|
rx_crc <= 1'b0;
|
else if (reset_mode | go_rx_crc_lim | error_frame)
|
// else if (reset_mode | go_rx_crc_lim | error_frame)
|
|
else if (reset_mode | go_rx_crc_lim | go_error_frame)
|
rx_crc <=#Tp 1'b0;
|
rx_crc <=#Tp 1'b0;
|
else if (go_rx_crc)
|
else if (go_rx_crc)
|
rx_crc <=#Tp 1'b1;
|
rx_crc <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 838... |
Line 867... |
// Rx crc delimiter state
|
// Rx crc delimiter state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_crc_lim <= 1'b0;
|
rx_crc_lim <= 1'b0;
|
else if (reset_mode | go_rx_ack | error_frame)
|
// else if (reset_mode | go_rx_ack | error_frame)
|
|
else if (reset_mode | go_rx_ack | go_error_frame)
|
rx_crc_lim <=#Tp 1'b0;
|
rx_crc_lim <=#Tp 1'b0;
|
else if (go_rx_crc_lim)
|
else if (go_rx_crc_lim)
|
rx_crc_lim <=#Tp 1'b1;
|
rx_crc_lim <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 850... |
Line 880... |
// Rx ack state
|
// Rx ack state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_ack <= 1'b0;
|
rx_ack <= 1'b0;
|
else if (reset_mode | go_rx_ack_lim | error_frame)
|
// else if (reset_mode | go_rx_ack_lim | error_frame)
|
|
else if (reset_mode | go_rx_ack_lim | go_error_frame)
|
rx_ack <=#Tp 1'b0;
|
rx_ack <=#Tp 1'b0;
|
else if (go_rx_ack)
|
else if (go_rx_ack)
|
rx_ack <=#Tp 1'b1;
|
rx_ack <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 862... |
Line 893... |
// Rx ack delimiter state
|
// Rx ack delimiter state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_ack_lim <= 1'b0;
|
rx_ack_lim <= 1'b0;
|
else if (reset_mode | go_rx_eof | error_frame)
|
// else if (reset_mode | go_rx_eof | error_frame)
|
|
else if (reset_mode | go_rx_eof | go_error_frame)
|
rx_ack_lim <=#Tp 1'b0;
|
rx_ack_lim <=#Tp 1'b0;
|
else if (go_rx_ack_lim)
|
else if (go_rx_ack_lim)
|
rx_ack_lim <=#Tp 1'b1;
|
rx_ack_lim <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 874... |
Line 906... |
// Rx eof state
|
// Rx eof state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_eof <= 1'b0;
|
rx_eof <= 1'b0;
|
else if (go_rx_inter | error_frame | go_overload_frame)
|
// else if (go_rx_inter | error_frame | go_overload_frame)
|
|
else if (go_rx_inter | go_error_frame | go_overload_frame)
|
rx_eof <=#Tp 1'b0;
|
rx_eof <=#Tp 1'b0;
|
else if (go_rx_eof)
|
else if (go_rx_eof)
|
rx_eof <=#Tp 1'b1;
|
rx_eof <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 1155... |
Line 1188... |
end
|
end
|
|
|
|
|
|
|
// Rule 5 (Fault confinement).
|
// Rule 5 (Fault confinement).
|
assign rule5 = (~node_error_passive) & bit_err & (error_frame & (error_cnt1 < 3'd7) |
|
assign rule5 = bit_err & ( (~node_error_passive) & error_frame & (error_cnt1 < 3'd7)
|
overload_frame & (overload_cnt1 < 3'd7) );
|
|
|
|
overload_frame & (overload_cnt1 < 3'd7)
|
|
);
|
|
|
// Rule 3 exception 1 - first part (Fault confinement).
|
// Rule 3 exception 1 - first part (Fault confinement).
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
| Line 1429... |
Line 1464... |
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
error_flag_over_blocked <= 1'b0;
|
error_flag_over_latched <= 1'b0;
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
error_flag_over_blocked <=#Tp 1'b0;
|
error_flag_over_latched <=#Tp 1'b0;
|
else if (error_flag_over)
|
else if (error_flag_over)
|
error_flag_over_blocked <=#Tp 1'b1;
|
error_flag_over_latched <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
enable_error_cnt2 <= 1'b0;
|
enable_error_cnt2 <= 1'b0;
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
| Line 1540... |
Line 1574... |
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
|
overload_request_cnt <= 2'b0;
|
|
else if (reset_mode | go_error_frame | go_rx_id1)
|
|
overload_request_cnt <=#Tp 2'b0;
|
|
else if (overload_request & overload_frame)
|
|
overload_request_cnt <=#Tp overload_request_cnt + 1'b1;
|
|
end
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
|
begin
|
|
if (rst)
|
overload_frame_blocked <= 1'b0;
|
overload_frame_blocked <= 1'b0;
|
else if (reset_mode | go_error_frame | go_rx_id1)
|
else if (reset_mode | go_error_frame | go_rx_id1)
|
overload_frame_blocked <=#Tp 1'b0;
|
overload_frame_blocked <=#Tp 1'b0;
|
else if (go_overload_frame & overload_frame) // This is a second sequential overload
|
else if (overload_request & overload_frame & overload_request_cnt == 2'h2) // This is a second sequential overload_request
|
overload_frame_blocked <=#Tp 1'b1;
|
overload_frame_blocked <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
assign send_ack = (~tx_state) & rx_ack & (~err) & (~listen_only_mode);
|
assign send_ack = (~tx_state) & rx_ack & (~err) & (~listen_only_mode);
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
reg tx_next;
|
|
always @ (reset_mode or tx_state or bit_de_stuff_tx or tx_bit or tx_q or
|
|
send_ack or overload_frame or overload_cnt1 or error_frame or error_cnt1 or
|
|
node_error_passive)
|
begin
|
begin
|
if (rst)
|
if (reset_mode) // Reset
|
tx <= 1'b1;
|
tx_next = 1'b1;
|
else if (reset_mode) // Reset
|
else
|
tx <=#Tp 1'b1;
|
|
else if (tx_point)
|
|
begin
|
begin
|
if (tx_state) // Transmitting message
|
if (tx_state) // Transmitting message
|
tx <=#Tp ((~bit_de_stuff_tx) & tx_bit) | (bit_de_stuff_tx & (~tx_q));
|
tx_next = ((~bit_de_stuff_tx) & tx_bit) | (bit_de_stuff_tx & (~tx_q));
|
else if (send_ack) // Acknowledge
|
else if (send_ack) // Acknowledge
|
tx <=#Tp 1'b0;
|
tx_next = 1'b0;
|
else if (overload_frame) // Transmitting overload frame
|
else if (overload_frame) // Transmitting overload frame
|
begin
|
begin
|
if (overload_cnt1 < 3'd6)
|
if (overload_cnt1 < 3'd6)
|
tx <=#Tp 1'b0;
|
tx_next = 1'b0;
|
else
|
else
|
tx <=#Tp 1'b1;
|
tx_next = 1'b1;
|
end
|
end
|
else if (error_frame) // Transmitting error frame
|
else if (error_frame) // Transmitting error frame
|
begin
|
begin
|
if (error_cnt1 < 3'd6)
|
if (error_cnt1 < 3'd6)
|
begin
|
begin
|
if (node_error_passive)
|
if (node_error_passive)
|
tx <=#Tp 1'b1;
|
tx_next = 1'b1;
|
else
|
else
|
tx <=#Tp 1'b0;
|
tx_next = 1'b0;
|
end
|
end
|
else
|
else
|
tx <=#Tp 1'b1;
|
tx_next = 1'b1;
|
end
|
end
|
else
|
else
|
tx <=#Tp 1'b1;
|
tx_next = 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
|
begin
|
|
if (rst)
|
|
tx <= 1'b1;
|
|
else if (tx_point)
|
|
tx <=#Tp tx_next;
|
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
tx_q <=#Tp 1'b0;
|
tx_q <=#Tp 1'b0;
|
| Line 1758... |
Line 1812... |
begin
|
begin
|
if (rst)
|
if (rst)
|
transmitter <= 1'b0;
|
transmitter <= 1'b0;
|
else if (go_tx)
|
else if (go_tx)
|
transmitter <=#Tp 1'b1;
|
transmitter <=#Tp 1'b1;
|
else if ((reset_mode | go_rx_inter ) | ((~tx_state) & tx_state_q))
|
// else if ((reset_mode | go_rx_inter ) | ((~tx_state) & tx_state_q))
|
|
else if (reset_mode | go_rx_idle)
|
transmitter <=#Tp 1'b0;
|
transmitter <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
|
|
| Line 1770... |
Line 1825... |
// Node might be both transmitter or receiver (sending error or overload frame)
|
// Node might be both transmitter or receiver (sending error or overload frame)
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
transmitting <= 1'b0;
|
transmitting <= 1'b0;
|
else if (go_error_frame | go_overload_frame | go_tx)
|
// else if (go_error_frame | go_overload_frame | go_tx)
|
|
else if (go_error_frame | go_overload_frame | go_tx | send_ack)
|
transmitting <=#Tp 1'b1;
|
transmitting <=#Tp 1'b1;
|
else if (reset_mode | go_rx_idle | (go_rx_id1 & (~tx_state)) | (arbitration_lost & tx_state))
|
else if (reset_mode | go_rx_idle | (go_rx_id1 & (~tx_state)) | (arbitration_lost & tx_state) | rx_ack_lim)
|
transmitting <=#Tp 1'b0;
|
transmitting <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
suspend <= 1'b0;
|
suspend <= 1'b0;
|
else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))
|
else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))
|
suspend <=#Tp 1'b0;
|
suspend <=#Tp 1'b0;
|
else if (go_rx_inter & transmitter & node_error_passive)
|
// else if (go_rx_inter & transmitter & node_error_passive)
|
|
else if (rx_inter & transmitter & node_error_passive)
|
suspend <=#Tp 1'b1;
|
suspend <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
| Line 1893... |
Line 1950... |
rx_err_cnt <=#Tp 9'h0;
|
rx_err_cnt <=#Tp 9'h0;
|
else
|
else
|
begin
|
begin
|
if (~listen_only_mode)
|
if (~listen_only_mode)
|
begin
|
begin
|
if ((~transmitter) & rx_ack & (~err) & (rx_err_cnt > 9'h0))
|
if (((~transmitter) | arbitration_lost) & go_rx_ack_lim & (~go_error_frame) & (rx_err_cnt > 9'h0))
|
begin
|
begin
|
if (rx_err_cnt > 9'd127)
|
if (rx_err_cnt > 9'd127)
|
rx_err_cnt <=#Tp 9'd127;
|
rx_err_cnt <=#Tp 9'd127;
|
else
|
else
|
rx_err_cnt <=#Tp rx_err_cnt - 1'b1;
|
rx_err_cnt <=#Tp rx_err_cnt - 1'b1;
|
end
|
end
|
else if ((rx_err_cnt < 9'd248) & (~transmitter)) // 248 + 8 = 256
|
else if ((rx_err_cnt < 9'd248) & (~transmitter)) // 248 + 8 = 256
|
begin
|
begin
|
if (go_error_frame & (~rule5)) // 1 (rule 5 is just the opposite then rule 1 exception
|
if (go_error_frame & (~rule5)) // 1 (rule 5 is just the opposite then rule 1 exception
|
rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
|
rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
|
else if ( (error_frame & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7) & (~rx_err_cnt_blocked) ) | // 2
|
// else if ( (error_frame & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7) & (~rx_err_cnt_blocked) ) | // 2
|
|
else if ( (error_flag_over_latched & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7) & (~rx_err_cnt_blocked) ) | // 2
|
(go_error_frame & rule5 ) | // 5
|
(go_error_frame & rule5 ) | // 5
|
(error_frame & sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) // 6
|
(error_frame & sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) // 6
|
)
|
)
|
rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
|
rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
|
end
|
end
|
| Line 1931... |
Line 1989... |
tx_err_cnt <=#Tp tx_err_cnt - 1'h1;
|
tx_err_cnt <=#Tp tx_err_cnt - 1'h1;
|
else if (transmitter)
|
else if (transmitter)
|
begin
|
begin
|
if ( (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) | // 6
|
if ( (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) | // 6
|
(go_error_frame & rule5 ) | // 4 (rule 5 is the same as rule 4)
|
(go_error_frame & rule5 ) | // 4 (rule 5 is the same as rule 4)
|
(error_flag_over & (~error_flag_over_blocked) & (~rule3_exc1_2) & (~rule3_exc2) ) // 3
|
// (error_flag_over & (~error_flag_over_latched) & (~rule3_exc1_2) & (~rule3_exc2) ) // 3
|
|
(go_error_frame & (~(transmitter & node_error_passive & ack_err)) ) // 3 ?
|
)
|
)
|
tx_err_cnt <=#Tp tx_err_cnt + 4'h8;
|
tx_err_cnt <=#Tp tx_err_cnt + 4'h8;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_err_cnt_blocked <= 1'b0;
|
rx_err_cnt_blocked <= 1'b0;
|
else if (reset_mode | error_frame_ended)
|
else if (reset_mode | error_frame_ended)
|
