| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.43 2003/09/25 18:55:49 mohor
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// Synchronization changed, error counters fixed.
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//
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// Revision 1.42 2003/08/29 07:01:14 mohor
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// Revision 1.42 2003/08/29 07:01:14 mohor
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// When detecting bus-free, signal bus_free_cnt_en was cleared to zero
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// When detecting bus-free, signal bus_free_cnt_en was cleared to zero
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// although the last sampled bit was zero instead of one.
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// although the last sampled bit was zero instead of one.
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//
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//
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// Revision 1.41 2003/07/18 15:23:31 tadejm
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// Revision 1.41 2003/07/18 15:23:31 tadejm
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| Line 257... |
Line 260... |
rx_idle,
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rx_idle,
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transmitting,
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transmitting,
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transmitter,
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transmitter,
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go_rx_inter,
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go_rx_inter,
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not_first_bit_of_inter,
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not_first_bit_of_inter,
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rx_inter,
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set_reset_mode,
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set_reset_mode,
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node_bus_off,
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node_bus_off,
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error_status,
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error_status,
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rx_err_cnt,
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rx_err_cnt,
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tx_err_cnt,
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tx_err_cnt,
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| Line 389... |
Line 393... |
output rx_idle;
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output rx_idle;
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output transmitting;
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output transmitting;
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output transmitter;
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output transmitter;
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output go_rx_inter;
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output go_rx_inter;
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output not_first_bit_of_inter;
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output not_first_bit_of_inter;
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output rx_inter;
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output set_reset_mode;
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output set_reset_mode;
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output node_bus_off;
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output node_bus_off;
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output error_status;
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output error_status;
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output [8:0] rx_err_cnt;
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output [8:0] rx_err_cnt;
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output [8:0] tx_err_cnt;
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output [8:0] tx_err_cnt;
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| Line 688... |
Line 693... |
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assign go_error_frame = (form_err | stuff_err | bit_err | ack_err | (crc_err & go_rx_eof));
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assign go_error_frame = (form_err | stuff_err | bit_err | ack_err | (crc_err & go_rx_eof));
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assign error_frame_ended = (error_cnt2 == 3'd7) & tx_point;
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assign error_frame_ended = (error_cnt2 == 3'd7) & tx_point;
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assign overload_frame_ended = (overload_cnt2 == 3'd7) & tx_point;
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assign overload_frame_ended = (overload_cnt2 == 3'd7) & tx_point;
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assign go_overload_frame = ( ((sample_point & rx_eof & (eof_cnt == 3'd6)) | error_frame_ended | overload_frame_ended) & overload_request |
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//assign go_overload_frame = ( ((sample_point & rx_eof & (eof_cnt == 3'd6)) | error_frame_ended | overload_frame_ended) & overload_request |
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assign go_overload_frame = ( ((sample_point & rx_eof & (eof_cnt == 3'd6)) | error_frame_ended | overload_frame_ended) & (overload_request | (~sampled_bit)) |
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sample_point & (~sampled_bit) & rx_inter & (bit_cnt[1:0] < 2'd2) |
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sample_point & (~sampled_bit) & rx_inter & (bit_cnt[1:0] < 2'd2) |
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sample_point & (~sampled_bit) & ((error_cnt2 == 3'd7) | (overload_cnt2 == 3'd7))
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sample_point & (~sampled_bit) & ((error_cnt2 == 3'd7) | (overload_cnt2 == 3'd7))
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)
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)
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& (~overload_frame_blocked)
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& (~overload_frame_blocked)
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;
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;
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| Line 1156... |
Line 1162... |
crc_err <=#Tp 1'b0;
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crc_err <=#Tp 1'b0;
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end
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end
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// Conditions for form error
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// Conditions for form error
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assign form_err = sample_point & ( ((~bit_de_stuff) & rx_ide & sampled_bit & (~rtr1) ) |
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assign form_err = sample_point & ( ((~bit_de_stuff) & rx_crc_lim & (~sampled_bit) ) |
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((~bit_de_stuff) & rx_crc_lim & (~sampled_bit) ) |
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( rx_ack_lim & (~sampled_bit) ) |
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( rx_ack_lim & (~sampled_bit) ) |
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((eof_cnt < 3'd6)& rx_eof & (~sampled_bit) & (~tx_state) ) |
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((eof_cnt < 3'd6)& rx_eof & (~sampled_bit) & (~tx_state) ) |
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( & rx_eof & (~sampled_bit) & tx_state )
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( & rx_eof & (~sampled_bit) & tx_state )
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);
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);
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| Line 1210... |
Line 1215... |
// Rule 3 exception 1 - second part (Fault confinement).
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// Rule 3 exception 1 - second part (Fault confinement).
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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rule3_exc1_2 <= 1'b0;
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rule3_exc1_2 <= 1'b0;
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else if (reset_mode | error_flag_over)
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// else if (reset_mode | error_flag_over)
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else if (reset_mode | go_error_frame | rule3_exc1_2)
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rule3_exc1_2 <=#Tp 1'b0;
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rule3_exc1_2 <=#Tp 1'b0;
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else if (rule3_exc1_1)
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else if (rule3_exc1_1 & (error_cnt1 < 3'd7) & sample_point & (~sampled_bit))
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rule3_exc1_2 <=#Tp 1'b1;
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rule3_exc1_2 <=#Tp 1'b1;
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else if ((error_cnt1 < 3'd7) & sample_point & (~sampled_bit))
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rule3_exc1_2 <=#Tp 1'b0;
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end
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end
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// Rule 3 exception 2 (Fault confinement).
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// Rule 3 exception 2 (Fault confinement).
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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| Line 1598... |
Line 1602... |
assign send_ack = (~tx_state) & rx_ack & (~err) & (~listen_only_mode);
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assign send_ack = (~tx_state) & rx_ack & (~err) & (~listen_only_mode);
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reg tx_next;
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reg tx_next;
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always @ (reset_mode or tx_state or bit_de_stuff_tx or tx_bit or tx_q or
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always @ (reset_mode or tx_state or bit_de_stuff_tx or tx_bit or tx_q or
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send_ack or overload_frame or overload_cnt1 or error_frame or error_cnt1 or
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//always @ (reset_mode or go_tx or tx_state or bit_de_stuff_tx or tx_bit or tx_q or
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node_error_passive)
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send_ack or go_overload_frame or overload_frame or overload_cnt1 or
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go_error_frame or error_frame or error_cnt1 or node_error_passive)
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begin
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begin
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if (reset_mode) // Reset
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if (reset_mode) // Reset
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tx_next = 1'b1;
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tx_next = 1'b1;
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else
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else
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begin
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begin
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if (tx_state) // Transmitting message
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if (go_error_frame | error_frame) // Transmitting error frame
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tx_next = ((~bit_de_stuff_tx) & tx_bit) | (bit_de_stuff_tx & (~tx_q));
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else if (send_ack) // Acknowledge
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tx_next = 1'b0;
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else if (overload_frame) // Transmitting overload frame
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begin
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if (overload_cnt1 < 3'd6)
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tx_next = 1'b0;
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else
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tx_next = 1'b1;
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end
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else if (error_frame) // Transmitting error frame
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begin
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begin
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if (error_cnt1 < 3'd6)
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if (error_cnt1 < 3'd6)
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begin
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begin
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if (node_error_passive)
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if (node_error_passive)
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tx_next = 1'b1;
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tx_next = 1'b1;
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| Line 1628... |
Line 1622... |
tx_next = 1'b0;
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tx_next = 1'b0;
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end
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end
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else
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else
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tx_next = 1'b1;
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tx_next = 1'b1;
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end
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end
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else if (go_overload_frame | overload_frame) // Transmitting overload frame
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begin
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if (overload_cnt1 < 3'd6)
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tx_next = 1'b0;
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else
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tx_next = 1'b1;
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end
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else if (tx_state) // Transmitting message
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// else if (go_tx | tx_state) // Transmitting message
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tx_next = ((~bit_de_stuff_tx) & tx_bit) | (bit_de_stuff_tx & (~tx_q));
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else if (send_ack) // Acknowledge
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tx_next = 1'b0;
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else
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else
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tx_next = 1'b1;
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tx_next = 1'b1;
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end
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end
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end
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end
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| Line 1776... |
Line 1782... |
// go_early_tx latched (for proper bit_de_stuff generation)
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// go_early_tx latched (for proper bit_de_stuff generation)
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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go_early_tx_latched <= 1'b0;
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go_early_tx_latched <= 1'b0;
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else if (tx_point_q)
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// else if (tx_point_q)
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else if (tx_point)
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go_early_tx_latched <=#Tp 1'b0;
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go_early_tx_latched <=#Tp 1'b0;
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else if (go_early_tx)
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else if (go_early_tx)
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go_early_tx_latched <=#Tp 1'b1;
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go_early_tx_latched <=#Tp 1'b1;
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end
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end
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| Line 1840... |
Line 1847... |
if (rst)
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if (rst)
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suspend <= 1'b0;
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suspend <= 1'b0;
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else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))
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else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))
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suspend <=#Tp 1'b0;
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suspend <=#Tp 1'b0;
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// else if (go_rx_inter & transmitter & node_error_passive)
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// else if (go_rx_inter & transmitter & node_error_passive)
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else if (rx_inter & transmitter & node_error_passive)
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else if (not_first_bit_of_inter & transmitter & node_error_passive)
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suspend <=#Tp 1'b1;
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suspend <=#Tp 1'b1;
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end
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end
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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| Line 1948... |
Line 1955... |
rx_err_cnt <=#Tp {1'b0, data_in};
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rx_err_cnt <=#Tp {1'b0, data_in};
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else if (set_reset_mode)
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else if (set_reset_mode)
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rx_err_cnt <=#Tp 9'h0;
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rx_err_cnt <=#Tp 9'h0;
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else
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else
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begin
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begin
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if (~listen_only_mode)
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if ((~listen_only_mode) & (~transmitter | arbitration_lost))
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begin
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begin
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if (((~transmitter) | arbitration_lost) & go_rx_ack_lim & (~go_error_frame) & (rx_err_cnt > 9'h0))
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if (go_rx_ack_lim & (~go_error_frame) & (~crc_err) & (rx_err_cnt > 9'h0))
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begin
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begin
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if (rx_err_cnt > 9'd127)
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if (rx_err_cnt > 9'd127)
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rx_err_cnt <=#Tp 9'd127;
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rx_err_cnt <=#Tp 9'd127;
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else
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else
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rx_err_cnt <=#Tp rx_err_cnt - 1'b1;
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rx_err_cnt <=#Tp rx_err_cnt - 1'b1;
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end
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end
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else if ((rx_err_cnt < 9'd248) & (~transmitter)) // 248 + 8 = 256
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else if (rx_err_cnt < 9'd248) // 248 + 8 = 256
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begin
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begin
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if (go_error_frame & (~rule5)) // 1 (rule 5 is just the opposite then rule 1 exception
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if (go_error_frame & (~rule5)) // 1 (rule 5 is just the opposite then rule 1 exception
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rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
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rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
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// else if ( (error_frame & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7) & (~rx_err_cnt_blocked) ) | // 2
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else if ( (error_flag_over & (~error_flag_over_latched) & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7) & (~rx_err_cnt_blocked) ) | // 2
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else if ( (error_flag_over_latched & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7) & (~rx_err_cnt_blocked) ) | // 2
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(go_error_frame & rule5 ) | // 5
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(go_error_frame & rule5 ) | // 5
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(error_frame & sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) // 6
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// (error_frame & sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) // 6
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(sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) // 6
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)
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)
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rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
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rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
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end
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end
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end
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end
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end
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end
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| Line 1985... |
Line 1992... |
begin
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begin
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if (set_reset_mode)
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if (set_reset_mode)
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tx_err_cnt <=#Tp 9'd127;
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tx_err_cnt <=#Tp 9'd127;
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else if ((tx_err_cnt > 9'd0) & (tx_successful | bus_free))
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else if ((tx_err_cnt > 9'd0) & (tx_successful | bus_free))
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tx_err_cnt <=#Tp tx_err_cnt - 1'h1;
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tx_err_cnt <=#Tp tx_err_cnt - 1'h1;
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else if (transmitter)
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else if (transmitter & (~arbitration_lost))
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begin
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begin
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if ( (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) | // 6
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if ( (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) | // 6
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(go_error_frame & rule5 ) | // 4 (rule 5 is the same as rule 4)
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(go_error_frame & rule5 ) | // 4 (rule 5 is the same as rule 4)
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// (error_flag_over & (~error_flag_over_latched) & (~rule3_exc1_2) & (~rule3_exc2) ) // 3
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// (error_flag_over & (~error_flag_over_latched) & (~rule3_exc1_2) & (~rule3_exc2) ) // 3
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(go_error_frame & (~(transmitter & node_error_passive & ack_err)) ) // 3 ?
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// (go_error_frame & (~(transmitter & node_error_passive & ack_err)) ) // 3 ?
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(go_error_frame & (~(transmitter & node_error_passive & ack_err)) ) | // 3
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(error_frame & rule3_exc1_2) // 3
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)
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)
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tx_err_cnt <=#Tp tx_err_cnt + 4'h8;
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tx_err_cnt <=#Tp tx_err_cnt + 4'h8;
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end
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end
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end
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end
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end
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end
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| Line 2014... |
Line 2023... |
|
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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node_error_passive <= 1'b0;
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node_error_passive <= 1'b0;
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else if ((rx_err_cnt < 128) & (tx_err_cnt < 9'd128) & error_frame_ended)
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// else if ((rx_err_cnt < 128) & (tx_err_cnt < 9'd128) & error_frame_ended)
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else if ((rx_err_cnt < 128) & (tx_err_cnt < 9'd128))
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node_error_passive <=#Tp 1'b0;
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node_error_passive <=#Tp 1'b0;
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else if (((rx_err_cnt >= 128) | (tx_err_cnt >= 9'd128)) & (error_frame_ended | go_error_frame | (~reset_mode) & reset_mode_q) & (~node_bus_off))
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else if (((rx_err_cnt >= 128) | (tx_err_cnt >= 9'd128)) & (error_frame_ended | go_error_frame | (~reset_mode) & reset_mode_q) & (~node_bus_off))
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node_error_passive <=#Tp 1'b1;
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node_error_passive <=#Tp 1'b1;
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end
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end
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