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Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.44 2003/09/30 00:55:12 mohor
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// Error counters fixed to be compatible with Bosch VHDL reference model.
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// Small synchronization changes.
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//
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// Revision 1.43 2003/09/25 18:55:49 mohor
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// Revision 1.43 2003/09/25 18:55:49 mohor
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// Synchronization changed, error counters fixed.
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// Synchronization changed, error counters fixed.
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//
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//
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// Revision 1.42 2003/08/29 07:01:14 mohor
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// Revision 1.42 2003/08/29 07:01:14 mohor
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// When detecting bus-free, signal bus_free_cnt_en was cleared to zero
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// When detecting bus-free, signal bus_free_cnt_en was cleared to zero
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| Line 665... |
Line 669... |
wire bit_err_exc1;
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wire bit_err_exc1;
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wire bit_err_exc2;
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wire bit_err_exc2;
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wire bit_err_exc3;
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wire bit_err_exc3;
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wire bit_err_exc4;
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wire bit_err_exc4;
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wire bit_err_exc5;
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wire bit_err_exc5;
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wire bit_err_exc6;
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wire error_flag_over;
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wire error_flag_over;
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wire overload_flag_over;
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wire overload_flag_over;
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wire [5:0] limited_tx_cnt_ext;
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wire [5:0] limited_tx_cnt_ext;
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wire [5:0] limited_tx_cnt_std;
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wire [5:0] limited_tx_cnt_std;
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| Line 693... |
Line 698... |
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assign go_error_frame = (form_err | stuff_err | bit_err | ack_err | (crc_err & go_rx_eof));
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assign go_error_frame = (form_err | stuff_err | bit_err | ack_err | (crc_err & go_rx_eof));
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assign error_frame_ended = (error_cnt2 == 3'd7) & tx_point;
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assign error_frame_ended = (error_cnt2 == 3'd7) & tx_point;
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assign overload_frame_ended = (overload_cnt2 == 3'd7) & tx_point;
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assign overload_frame_ended = (overload_cnt2 == 3'd7) & tx_point;
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//assign go_overload_frame = ( ((sample_point & rx_eof & (eof_cnt == 3'd6)) | error_frame_ended | overload_frame_ended) & overload_request |
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//assign go_overload_frame = ( ((sample_point & rx_eof & (eof_cnt == 3'd6)) | error_frame_ended | overload_frame_ended) & (overload_request | (~sampled_bit)) |
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assign go_overload_frame = ( ((sample_point & rx_eof & (eof_cnt == 3'd6)) | error_frame_ended | overload_frame_ended) & (overload_request | (~sampled_bit)) |
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//assign go_overload_frame = ( sample_point & ((~sampled_bit) | overload_request) & (rx_eof & (eof_cnt == 3'd6) | error_frame_ended | overload_frame_ended) |
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assign go_overload_frame = ( sample_point & ((~sampled_bit) | overload_request) & (rx_eof & (~transmitter) & (eof_cnt == 3'd6) | error_frame_ended | overload_frame_ended) |
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sample_point & (~sampled_bit) & rx_inter & (bit_cnt[1:0] < 2'd2) |
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sample_point & (~sampled_bit) & rx_inter & (bit_cnt[1:0] < 2'd2) |
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sample_point & (~sampled_bit) & ((error_cnt2 == 3'd7) | (overload_cnt2 == 3'd7))
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sample_point & (~sampled_bit) & ((error_cnt2 == 3'd7) | (overload_cnt2 == 3'd7))
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)
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)
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& (~overload_frame_blocked)
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& (~overload_frame_blocked)
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;
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;
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| Line 712... |
Line 718... |
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assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
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assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
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assign limited_data_len = (data_len < 4'h8)? data_len : 4'h8;
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assign limited_data_len = (data_len < 4'h8)? data_len : 4'h8;
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assign ack_err = rx_ack & sample_point & sampled_bit & tx_state & (~self_test_mode);
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assign ack_err = rx_ack & sample_point & sampled_bit & tx_state & (~self_test_mode);
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assign bit_err = (tx_state | error_frame | overload_frame | rx_ack) & sample_point & (tx != sampled_bit) & (~bit_err_exc1) & (~bit_err_exc2) & (~bit_err_exc3) & (~bit_err_exc4) & (~bit_err_exc5);
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assign bit_err = (tx_state | error_frame | overload_frame | rx_ack) & sample_point & (tx != sampled_bit) & (~bit_err_exc1) & (~bit_err_exc2) & (~bit_err_exc3) & (~bit_err_exc4) & (~bit_err_exc5) & (~bit_err_exc6);
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assign bit_err_exc1 = tx_state & arbitration_field & tx;
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assign bit_err_exc1 = tx_state & arbitration_field & tx;
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assign bit_err_exc2 = rx_ack & tx;
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assign bit_err_exc2 = rx_ack & tx;
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assign bit_err_exc3 = error_frame & node_error_passive & (error_cnt1 < 3'd7);
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assign bit_err_exc3 = error_frame & node_error_passive & (error_cnt1 < 3'd7);
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assign bit_err_exc4 = (error_frame & (error_cnt1 == 3'd7) & (~enable_error_cnt2)) | (overload_frame & (overload_cnt1 == 3'd7) & (~enable_overload_cnt2));
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assign bit_err_exc4 = (error_frame & (error_cnt1 == 3'd7) & (~enable_error_cnt2)) | (overload_frame & (overload_cnt1 == 3'd7) & (~enable_overload_cnt2));
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assign bit_err_exc5 = (error_frame & (error_cnt2 == 3'd7)) | (overload_frame & (overload_cnt2 == 3'd7));
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assign bit_err_exc5 = (error_frame & (error_cnt2 == 3'd7)) | (overload_frame & (overload_cnt2 == 3'd7));
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assign bit_err_exc6 = (eof_cnt == 3'd6) & rx_eof & (~transmitter);
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assign arbitration_field = rx_id1 | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2;
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assign arbitration_field = rx_id1 | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2;
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assign last_bit_of_inter = rx_inter & (bit_cnt[1:0] == 2'd2);
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assign last_bit_of_inter = rx_inter & (bit_cnt[1:0] == 2'd2);
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assign not_first_bit_of_inter = rx_inter & (bit_cnt[1:0] != 2'd0);
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assign not_first_bit_of_inter = rx_inter & (bit_cnt[1:0] != 2'd0);
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| Line 1164... |
Line 1171... |
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// Conditions for form error
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// Conditions for form error
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assign form_err = sample_point & ( ((~bit_de_stuff) & rx_crc_lim & (~sampled_bit) ) |
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assign form_err = sample_point & ( ((~bit_de_stuff) & rx_crc_lim & (~sampled_bit) ) |
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( rx_ack_lim & (~sampled_bit) ) |
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( rx_ack_lim & (~sampled_bit) ) |
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((eof_cnt < 3'd6)& rx_eof & (~sampled_bit) & (~tx_state) ) |
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// ((eof_cnt < 3'd6)& rx_eof & (~sampled_bit) & (~tx_state) ) |
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( & rx_eof & (~sampled_bit) & tx_state )
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// ( & rx_eof & (~sampled_bit) & tx_state )
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// ((eof_cnt < 3'd6)& rx_eof & (~sampled_bit) & (~tx_state) )
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((eof_cnt < 3'd6)& rx_eof & (~sampled_bit) & (~transmitter) ) |
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( & rx_eof & (~sampled_bit) & transmitter )
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);
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);
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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| Line 1757... |
Line 1767... |
else if (go_early_tx | (tx_point & tx_state & (~bit_de_stuff_tx)))
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else if (go_early_tx | (tx_point & tx_state & (~bit_de_stuff_tx)))
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tx_pointer <=#Tp tx_pointer + 1'b1;
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tx_pointer <=#Tp tx_pointer + 1'b1;
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end
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end
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//assign tx_successful = transmitter & go_rx_inter & ((~error_frame_ended) & (~overload_frame_ended) & (~arbitration_lost) | single_shot_transmission);
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//assign tx_successful = transmitter & go_rx_inter & (~error_frame_ended) & (~overload_frame_ended) & (~arbitration_lost);
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assign tx_successful = transmitter & go_rx_inter & (~error_frame_ended) & (~overload_frame_ended) & (~arbitration_lost);
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assign tx_successful = transmitter & go_rx_inter & (~go_error_frame) & (~error_frame_ended) & (~overload_frame_ended) & (~arbitration_lost);
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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| Line 1891... |
Line 1901... |
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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arbitration_lost <= 1'b0;
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arbitration_lost <= 1'b0;
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else if (go_rx_idle | error_frame | reset_mode)
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// else if (go_rx_idle | error_frame | reset_mode)
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else if (go_rx_idle | error_frame_ended | reset_mode)
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arbitration_lost <=#Tp 1'b0;
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arbitration_lost <=#Tp 1'b0;
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else if (tx_state & sample_point & tx & arbitration_field)
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// else if (tx_state & sample_point & tx & arbitration_field)
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else if (transmitter & sample_point & tx & arbitration_field)
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arbitration_lost <=#Tp (~sampled_bit);
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arbitration_lost <=#Tp (~sampled_bit);
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end
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end
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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| Line 1955... |
Line 1967... |
rx_err_cnt <=#Tp {1'b0, data_in};
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rx_err_cnt <=#Tp {1'b0, data_in};
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else if (set_reset_mode)
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else if (set_reset_mode)
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rx_err_cnt <=#Tp 9'h0;
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rx_err_cnt <=#Tp 9'h0;
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else
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else
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begin
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begin
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// if ((~listen_only_mode) & (~transmitter | arbitration_lost | suspend))
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if ((~listen_only_mode) & (~transmitter | arbitration_lost))
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if ((~listen_only_mode) & (~transmitter | arbitration_lost))
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begin
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begin
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if (go_rx_ack_lim & (~go_error_frame) & (~crc_err) & (rx_err_cnt > 9'h0))
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if (go_rx_ack_lim & (~go_error_frame) & (~crc_err) & (rx_err_cnt > 9'h0))
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begin
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begin
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if (rx_err_cnt > 9'd127)
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if (rx_err_cnt > 9'd127)
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rx_err_cnt <=#Tp 9'd127;
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rx_err_cnt <=#Tp 9'd127;
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else
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else
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rx_err_cnt <=#Tp rx_err_cnt - 1'b1;
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rx_err_cnt <=#Tp rx_err_cnt - 1'b1;
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end
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end
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else if (rx_err_cnt < 9'd248) // 248 + 8 = 256
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else if (rx_err_cnt < 9'd128)
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begin
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begin
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if (go_error_frame & (~rule5)) // 1 (rule 5 is just the opposite then rule 1 exception
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if (go_error_frame & (~rule5)) // 1 (rule 5 is just the opposite then rule 1 exception
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rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
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rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
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else if ( (error_flag_over & (~error_flag_over_latched) & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7) & (~rx_err_cnt_blocked) ) | // 2
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// else if ( (error_flag_over & (~error_flag_over_latched) & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7) & (~rx_err_cnt_blocked) ) | // 2
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// else if ( (error_flag_over & (~error_flag_over_latched) & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7) ) | // 2
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else if ( (error_flag_over & (~error_flag_over_latched) & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7) ) | // 2
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(go_error_frame & rule5 ) | // 5
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(go_error_frame & rule5 ) | // 5
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// (error_frame & sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) // 6
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// (error_frame & sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) // 6
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(sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) // 6
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(sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) // 6
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)
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)
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rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
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rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
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| Line 1992... |
Line 2007... |
begin
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begin
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if (set_reset_mode)
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if (set_reset_mode)
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tx_err_cnt <=#Tp 9'd127;
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tx_err_cnt <=#Tp 9'd127;
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else if ((tx_err_cnt > 9'd0) & (tx_successful | bus_free))
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else if ((tx_err_cnt > 9'd0) & (tx_successful | bus_free))
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tx_err_cnt <=#Tp tx_err_cnt - 1'h1;
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tx_err_cnt <=#Tp tx_err_cnt - 1'h1;
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// else if (transmitter & (~arbitration_lost) & (~suspend))
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else if (transmitter & (~arbitration_lost))
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else if (transmitter & (~arbitration_lost))
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begin
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begin
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if ( (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) | // 6
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if ( (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) | // 6
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(go_error_frame & rule5 ) | // 4 (rule 5 is the same as rule 4)
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(go_error_frame & rule5 ) | // 4 (rule 5 is the same as rule 4)
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// (error_flag_over & (~error_flag_over_latched) & (~rule3_exc1_2) & (~rule3_exc2) ) // 3
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(go_error_frame & (~(transmitter & node_error_passive & ack_err)) & (~(transmitter & stuff_err & arbitration_field & sample_point & tx & (~sampled_bit))) ) | // 3
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// (go_error_frame & (~(transmitter & node_error_passive & ack_err)) ) // 3 ?
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(error_frame & rule3_exc1_2 ) //| // 3
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(go_error_frame & (~(transmitter & node_error_passive & ack_err)) ) | // 3
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// (go_error_frame & (~(transmitter & stuff_err & arbitration_field & sample_point & tx & (~sampled_bit))) ) //
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(error_frame & rule3_exc1_2) // 3
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)
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)
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tx_err_cnt <=#Tp tx_err_cnt + 4'h8;
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tx_err_cnt <=#Tp tx_err_cnt + 4'h8;
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end
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end
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end
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end
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end
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end
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| Line 2011... |
Line 2026... |
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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rx_err_cnt_blocked <= 1'b0;
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rx_err_cnt_blocked <= 1'b0;
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else if (reset_mode | error_frame_ended)
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else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
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rx_err_cnt_blocked <=#Tp 1'b0;
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rx_err_cnt_blocked <=#Tp 1'b0;
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else if (sample_point & (error_cnt1 == 3'd7))
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else if (sample_point & (error_cnt1 == 3'd7))
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rx_err_cnt_blocked <=#Tp 1'b1;
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rx_err_cnt_blocked <=#Tp 1'b1;
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end
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end
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