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[/] [can/] [trunk/] [rtl/] [verilog/] [can_bsp.v] - Diff between revs 129 and 130
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| Rev 129 |
Rev 130 |
| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.45 2003/09/30 21:14:33 mohor
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// Error counters changed.
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//
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// Revision 1.44 2003/09/30 00:55:12 mohor
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// Revision 1.44 2003/09/30 00:55:12 mohor
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// Error counters fixed to be compatible with Bosch VHDL reference model.
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// Error counters fixed to be compatible with Bosch VHDL reference model.
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// Small synchronization changes.
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// Small synchronization changes.
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//
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//
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// Revision 1.43 2003/09/25 18:55:49 mohor
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// Revision 1.43 2003/09/25 18:55:49 mohor
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| Line 334... |
Line 337... |
send_ack
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send_ack
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/* Bist */
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/* Bist */
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`ifdef CAN_BIST
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`ifdef CAN_BIST
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,
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,
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scanb_rst,
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mbist_si_i,
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scanb_clk,
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mbist_so_o,
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scanb_si,
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mbist_ctrl_i
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scanb_so,
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scanb_en
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`endif
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`endif
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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| Line 467... |
Line 468... |
output go_tx;
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output go_tx;
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output send_ack;
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output send_ack;
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/* Bist */
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/* Bist */
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`ifdef CAN_BIST
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`ifdef CAN_BIST
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input scanb_rst;
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input mbist_si_i;
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input scanb_clk;
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output mbist_so_o;
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input scanb_si;
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input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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output scanb_so;
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input scanb_en;
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`endif
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`endif
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reg reset_mode_q;
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reg reset_mode_q;
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reg [5:0] bit_cnt;
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reg [5:0] bit_cnt;
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Line 1429... |
.info_empty(info_empty),
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.info_empty(info_empty),
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.info_cnt(rx_message_counter)
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.info_cnt(rx_message_counter)
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`ifdef CAN_BIST
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`ifdef CAN_BIST
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,
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,
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.scanb_rst(scanb_rst),
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.mbist_si_i(mbist_si_i),
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.scanb_clk(scanb_clk),
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.mbist_so_o(mbist_so_o),
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.scanb_si(scanb_si),
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.mbist_ctrl_i(mbist_ctrl_i)
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.scanb_so(scanb_so),
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.scanb_en(scanb_en)
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`endif
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`endif
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);
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);
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// Transmitting error frame.
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// Transmitting error frame.
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