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[/] [can/] [trunk/] [rtl/] [verilog/] [can_bsp.v] - Diff between revs 130 and 136

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Rev 130 Rev 136
Line 15... Line 15...
////  All additional information is available in the README.txt   ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
//// Copyright (C) 2002, 2003, 2004 Authors                       ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
Line 48... Line 48...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.46  2003/10/17 05:55:20  markom
 
// mbist signals updated according to newest convention
 
//
// Revision 1.45  2003/09/30 21:14:33  mohor
// Revision 1.45  2003/09/30 21:14:33  mohor
// Error counters changed.
// Error counters changed.
//
//
// Revision 1.44  2003/09/30 00:55:12  mohor
// Revision 1.44  2003/09/30 00:55:12  mohor
// Error counters fixed to be compatible with Bosch VHDL reference model.
// Error counters fixed to be compatible with Bosch VHDL reference model.
Line 286... Line 289...
  arbitration_lost_capture,
  arbitration_lost_capture,
  node_error_passive,
  node_error_passive,
  node_error_active,
  node_error_active,
  rx_message_counter,
  rx_message_counter,
 
 
 
 
 
 
  /* This section is for BASIC and EXTENDED mode */
  /* This section is for BASIC and EXTENDED mode */
  /* Acceptance code register */
  /* Acceptance code register */
  acceptance_code_0,
  acceptance_code_0,
 
 
  /* Acceptance mask register */
  /* Acceptance mask register */
Line 327... Line 328...
  /* End: Tx data registers */
  /* End: Tx data registers */
 
 
  /* Tx signal */
  /* Tx signal */
  tx,
  tx,
  tx_next,
  tx_next,
  tx_oen,
  bus_off_on,
 
 
  go_overload_frame,
  go_overload_frame,
  go_error_frame,
  go_error_frame,
  go_tx,
  go_tx,
  send_ack
  send_ack
Line 357... Line 358...
input   [7:0] addr;
input   [7:0] addr;
input   [7:0] data_in;
input   [7:0] data_in;
output  [7:0] data_out;
output  [7:0] data_out;
input         fifo_selected;
input         fifo_selected;
 
 
 
 
input         reset_mode;
input         reset_mode;
input         listen_only_mode;
input         listen_only_mode;
input         acceptance_filter_mode;
input         acceptance_filter_mode;
input         extended_mode;
input         extended_mode;
input         self_test_mode;
input         self_test_mode;
 
 
 
 
/* Command register */
/* Command register */
input         release_buffer;
input         release_buffer;
input         tx_request;
input         tx_request;
input         abort_tx;
input         abort_tx;
input         self_rx_request;
input         self_rx_request;
Line 459... Line 458...
/* End: Tx data registers */
/* End: Tx data registers */
 
 
/* Tx signal */
/* Tx signal */
output        tx;
output        tx;
output        tx_next;
output        tx_next;
output        tx_oen;
output        bus_off_on;
 
 
output        go_overload_frame;
output        go_overload_frame;
output        go_error_frame;
output        go_error_frame;
output        go_tx;
output        go_tx;
output        send_ack;
output        send_ack;
Line 697... Line 696...
 
 
assign go_error_frame = (form_err | stuff_err | bit_err | ack_err | (crc_err & go_rx_eof));
assign go_error_frame = (form_err | stuff_err | bit_err | ack_err | (crc_err & go_rx_eof));
assign error_frame_ended = (error_cnt2 == 3'd7) & tx_point;
assign error_frame_ended = (error_cnt2 == 3'd7) & tx_point;
assign overload_frame_ended = (overload_cnt2 == 3'd7) & tx_point;
assign overload_frame_ended = (overload_cnt2 == 3'd7) & tx_point;
 
 
//assign go_overload_frame = (   ((sample_point &  rx_eof  & (eof_cnt == 3'd6)) | error_frame_ended | overload_frame_ended) & (overload_request | (~sampled_bit)) | 
 
//assign go_overload_frame = (     sample_point & ((~sampled_bit) | overload_request) & (rx_eof  & (eof_cnt == 3'd6) | error_frame_ended | overload_frame_ended) | 
 
assign go_overload_frame = (     sample_point & ((~sampled_bit) | overload_request) & (rx_eof & (~transmitter) & (eof_cnt == 3'd6) | error_frame_ended | overload_frame_ended) |
assign go_overload_frame = (     sample_point & ((~sampled_bit) | overload_request) & (rx_eof & (~transmitter) & (eof_cnt == 3'd6) | error_frame_ended | overload_frame_ended) |
                                 sample_point & (~sampled_bit) & rx_inter & (bit_cnt[1:0] < 2'd2)                                                            |
                                 sample_point & (~sampled_bit) & rx_inter & (bit_cnt[1:0] < 2'd2)                                                            |
                                 sample_point & (~sampled_bit) & ((error_cnt2 == 3'd7) | (overload_cnt2 == 3'd7))
                                 sample_point & (~sampled_bit) & ((error_cnt2 == 3'd7) | (overload_cnt2 == 3'd7))
                           )
                           )
                           & (~overload_frame_blocked)
                           & (~overload_frame_blocked)
Line 736... Line 733...
// Rx idle state
// Rx idle state
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    rx_idle <= 1'b0;
    rx_idle <= 1'b0;
//  else if (reset_mode | go_rx_id1 | error_frame)
 
  else if (reset_mode | go_rx_id1 | go_error_frame)
  else if (reset_mode | go_rx_id1 | go_error_frame)
    rx_idle <=#Tp 1'b0;
    rx_idle <=#Tp 1'b0;
  else if (go_rx_idle)
  else if (go_rx_idle)
    rx_idle <=#Tp 1'b1;
    rx_idle <=#Tp 1'b1;
end
end
Line 749... Line 745...
// Rx id1 state
// Rx id1 state
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    rx_id1 <= 1'b0;
    rx_id1 <= 1'b0;
//  else if (reset_mode | go_rx_rtr1 | error_frame)
 
  else if (reset_mode | go_rx_rtr1 | go_error_frame)
  else if (reset_mode | go_rx_rtr1 | go_error_frame)
    rx_id1 <=#Tp 1'b0;
    rx_id1 <=#Tp 1'b0;
  else if (go_rx_id1)
  else if (go_rx_id1)
    rx_id1 <=#Tp 1'b1;
    rx_id1 <=#Tp 1'b1;
end
end
Line 762... Line 757...
// Rx rtr1 state
// Rx rtr1 state
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    rx_rtr1 <= 1'b0;
    rx_rtr1 <= 1'b0;
//  else if (reset_mode | go_rx_ide | error_frame)
 
  else if (reset_mode | go_rx_ide | go_error_frame)
  else if (reset_mode | go_rx_ide | go_error_frame)
    rx_rtr1 <=#Tp 1'b0;
    rx_rtr1 <=#Tp 1'b0;
  else if (go_rx_rtr1)
  else if (go_rx_rtr1)
    rx_rtr1 <=#Tp 1'b1;
    rx_rtr1 <=#Tp 1'b1;
end
end
Line 775... Line 769...
// Rx ide state
// Rx ide state
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    rx_ide <= 1'b0;
    rx_ide <= 1'b0;
//  else if (reset_mode | go_rx_r0 | go_rx_id2 | error_frame)
 
  else if (reset_mode | go_rx_r0 | go_rx_id2 | go_error_frame)
  else if (reset_mode | go_rx_r0 | go_rx_id2 | go_error_frame)
    rx_ide <=#Tp 1'b0;
    rx_ide <=#Tp 1'b0;
  else if (go_rx_ide)
  else if (go_rx_ide)
    rx_ide <=#Tp 1'b1;
    rx_ide <=#Tp 1'b1;
end
end
Line 788... Line 781...
// Rx id2 state
// Rx id2 state
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    rx_id2 <= 1'b0;
    rx_id2 <= 1'b0;
//  else if (reset_mode | go_rx_rtr2 | error_frame)
 
  else if (reset_mode | go_rx_rtr2 | go_error_frame)
  else if (reset_mode | go_rx_rtr2 | go_error_frame)
    rx_id2 <=#Tp 1'b0;
    rx_id2 <=#Tp 1'b0;
  else if (go_rx_id2)
  else if (go_rx_id2)
    rx_id2 <=#Tp 1'b1;
    rx_id2 <=#Tp 1'b1;
end
end
Line 801... Line 793...
// Rx rtr2 state
// Rx rtr2 state
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    rx_rtr2 <= 1'b0;
    rx_rtr2 <= 1'b0;
//  else if (reset_mode | go_rx_r1 | error_frame)
 
  else if (reset_mode | go_rx_r1 | go_error_frame)
  else if (reset_mode | go_rx_r1 | go_error_frame)
    rx_rtr2 <=#Tp 1'b0;
    rx_rtr2 <=#Tp 1'b0;
  else if (go_rx_rtr2)
  else if (go_rx_rtr2)
    rx_rtr2 <=#Tp 1'b1;
    rx_rtr2 <=#Tp 1'b1;
end
end
Line 814... Line 805...
// Rx r0 state
// Rx r0 state
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    rx_r1 <= 1'b0;
    rx_r1 <= 1'b0;
//  else if (reset_mode | go_rx_r0 | error_frame)
 
  else if (reset_mode | go_rx_r0 | go_error_frame)
  else if (reset_mode | go_rx_r0 | go_error_frame)
    rx_r1 <=#Tp 1'b0;
    rx_r1 <=#Tp 1'b0;
  else if (go_rx_r1)
  else if (go_rx_r1)
    rx_r1 <=#Tp 1'b1;
    rx_r1 <=#Tp 1'b1;
end
end
Line 827... Line 817...
// Rx r0 state
// Rx r0 state
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    rx_r0 <= 1'b0;
    rx_r0 <= 1'b0;
//  else if (reset_mode | go_rx_dlc | error_frame)
 
  else if (reset_mode | go_rx_dlc | go_error_frame)
  else if (reset_mode | go_rx_dlc | go_error_frame)
    rx_r0 <=#Tp 1'b0;
    rx_r0 <=#Tp 1'b0;
  else if (go_rx_r0)
  else if (go_rx_r0)
    rx_r0 <=#Tp 1'b1;
    rx_r0 <=#Tp 1'b1;
end
end
Line 840... Line 829...
// Rx dlc state
// Rx dlc state
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    rx_dlc <= 1'b0;
    rx_dlc <= 1'b0;
//  else if (reset_mode | go_rx_data | go_rx_crc | error_frame)
 
  else if (reset_mode | go_rx_data | go_rx_crc | go_error_frame)
  else if (reset_mode | go_rx_data | go_rx_crc | go_error_frame)
    rx_dlc <=#Tp 1'b0;
    rx_dlc <=#Tp 1'b0;
  else if (go_rx_dlc)
  else if (go_rx_dlc)
    rx_dlc <=#Tp 1'b1;
    rx_dlc <=#Tp 1'b1;
end
end
Line 853... Line 841...
// Rx data state
// Rx data state
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    rx_data <= 1'b0;
    rx_data <= 1'b0;
//  else if (reset_mode | go_rx_crc | error_frame)
 
  else if (reset_mode | go_rx_crc | go_error_frame)
  else if (reset_mode | go_rx_crc | go_error_frame)
    rx_data <=#Tp 1'b0;
    rx_data <=#Tp 1'b0;
  else if (go_rx_data)
  else if (go_rx_data)
    rx_data <=#Tp 1'b1;
    rx_data <=#Tp 1'b1;
end
end
Line 866... Line 853...
// Rx crc state
// Rx crc state
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    rx_crc <= 1'b0;
    rx_crc <= 1'b0;
//  else if (reset_mode | go_rx_crc_lim | error_frame)
 
  else if (reset_mode | go_rx_crc_lim | go_error_frame)
  else if (reset_mode | go_rx_crc_lim | go_error_frame)
    rx_crc <=#Tp 1'b0;
    rx_crc <=#Tp 1'b0;
  else if (go_rx_crc)
  else if (go_rx_crc)
    rx_crc <=#Tp 1'b1;
    rx_crc <=#Tp 1'b1;
end
end
Line 879... Line 865...
// Rx crc delimiter state
// Rx crc delimiter state
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    rx_crc_lim <= 1'b0;
    rx_crc_lim <= 1'b0;
//  else if (reset_mode | go_rx_ack | error_frame)
 
  else if (reset_mode | go_rx_ack | go_error_frame)
  else if (reset_mode | go_rx_ack | go_error_frame)
    rx_crc_lim <=#Tp 1'b0;
    rx_crc_lim <=#Tp 1'b0;
  else if (go_rx_crc_lim)
  else if (go_rx_crc_lim)
    rx_crc_lim <=#Tp 1'b1;
    rx_crc_lim <=#Tp 1'b1;
end
end
Line 892... Line 877...
// Rx ack state
// Rx ack state
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    rx_ack <= 1'b0;
    rx_ack <= 1'b0;
//  else if (reset_mode | go_rx_ack_lim | error_frame)
 
  else if (reset_mode | go_rx_ack_lim | go_error_frame)
  else if (reset_mode | go_rx_ack_lim | go_error_frame)
    rx_ack <=#Tp 1'b0;
    rx_ack <=#Tp 1'b0;
  else if (go_rx_ack)
  else if (go_rx_ack)
    rx_ack <=#Tp 1'b1;
    rx_ack <=#Tp 1'b1;
end
end
Line 905... Line 889...
// Rx ack delimiter state
// Rx ack delimiter state
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    rx_ack_lim <= 1'b0;
    rx_ack_lim <= 1'b0;
//  else if (reset_mode | go_rx_eof | error_frame)
 
  else if (reset_mode | go_rx_eof | go_error_frame)
  else if (reset_mode | go_rx_eof | go_error_frame)
    rx_ack_lim <=#Tp 1'b0;
    rx_ack_lim <=#Tp 1'b0;
  else if (go_rx_ack_lim)
  else if (go_rx_ack_lim)
    rx_ack_lim <=#Tp 1'b1;
    rx_ack_lim <=#Tp 1'b1;
end
end
Line 918... Line 901...
// Rx eof state
// Rx eof state
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    rx_eof <= 1'b0;
    rx_eof <= 1'b0;
//  else if (go_rx_inter | error_frame | go_overload_frame)
 
  else if (go_rx_inter | go_error_frame | go_overload_frame)
  else if (go_rx_inter | go_error_frame | go_overload_frame)
    rx_eof <=#Tp 1'b0;
    rx_eof <=#Tp 1'b0;
  else if (go_rx_eof)
  else if (go_rx_eof)
    rx_eof <=#Tp 1'b1;
    rx_eof <=#Tp 1'b1;
end
end
Line 1224... Line 1206...
// Rule 3 exception 1 - second part (Fault confinement).
// Rule 3 exception 1 - second part (Fault confinement).
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    rule3_exc1_2 <= 1'b0;
    rule3_exc1_2 <= 1'b0;
//  else if (reset_mode | error_flag_over)
 
  else if (reset_mode | go_error_frame | rule3_exc1_2)
  else if (reset_mode | go_error_frame | rule3_exc1_2)
    rule3_exc1_2 <=#Tp 1'b0;
    rule3_exc1_2 <=#Tp 1'b0;
  else if (rule3_exc1_1 & (error_cnt1 < 3'd7) & sample_point & (~sampled_bit))
  else if (rule3_exc1_1 & (error_cnt1 < 3'd7) & sample_point & (~sampled_bit))
    rule3_exc1_2 <=#Tp 1'b1;
    rule3_exc1_2 <=#Tp 1'b1;
end
end
Line 1608... Line 1589...
 
 
assign send_ack = (~tx_state) & rx_ack & (~err) & (~listen_only_mode);
assign send_ack = (~tx_state) & rx_ack & (~err) & (~listen_only_mode);
 
 
 
 
reg tx_next;
reg tx_next;
always @ (reset_mode or tx_state or bit_de_stuff_tx or tx_bit or tx_q or
always @ (reset_mode or node_bus_off or tx_state or bit_de_stuff_tx or tx_bit or tx_q or
//always @ (reset_mode or go_tx or tx_state or bit_de_stuff_tx or tx_bit or tx_q or
 
          send_ack or go_overload_frame or overload_frame or overload_cnt1 or
          send_ack or go_overload_frame or overload_frame or overload_cnt1 or
          go_error_frame or error_frame or error_cnt1 or node_error_passive)
          go_error_frame or error_frame or error_cnt1 or node_error_passive)
begin
begin
  if (reset_mode)                                                               // Reset
  if (reset_mode | node_bus_off)                                                // Reset or node_bus_off
    tx_next = 1'b1;
    tx_next = 1'b1;
  else
  else
    begin
    begin
      if (go_error_frame | error_frame)                                         // Transmitting error frame
      if (go_error_frame | error_frame)                                         // Transmitting error frame
        begin
        begin
Line 1637... Line 1617...
            tx_next = 1'b0;
            tx_next = 1'b0;
          else
          else
            tx_next = 1'b1;
            tx_next = 1'b1;
        end
        end
      else if (tx_state)                                                        // Transmitting message
      else if (tx_state)                                                        // Transmitting message
//      else if (go_tx | tx_state)                                                // Transmitting message
 
        tx_next = ((~bit_de_stuff_tx) & tx_bit) | (bit_de_stuff_tx & (~tx_q));
        tx_next = ((~bit_de_stuff_tx) & tx_bit) | (bit_de_stuff_tx & (~tx_q));
      else if (send_ack)                                                        // Acknowledge
      else if (send_ack)                                                        // Acknowledge
        tx_next = 1'b0;
        tx_next = 1'b0;
      else
      else
        tx_next = 1'b1;
        tx_next = 1'b1;
Line 1764... Line 1743...
  else if (go_early_tx | (tx_point & tx_state & (~bit_de_stuff_tx)))
  else if (go_early_tx | (tx_point & tx_state & (~bit_de_stuff_tx)))
    tx_pointer <=#Tp tx_pointer + 1'b1;
    tx_pointer <=#Tp tx_pointer + 1'b1;
end
end
 
 
 
 
//assign tx_successful = transmitter & go_rx_inter & (~error_frame_ended) & (~overload_frame_ended) & (~arbitration_lost);
 
assign tx_successful = transmitter & go_rx_inter & (~go_error_frame) & (~error_frame_ended) & (~overload_frame_ended) & (~arbitration_lost);
assign tx_successful = transmitter & go_rx_inter & (~go_error_frame) & (~error_frame_ended) & (~overload_frame_ended) & (~arbitration_lost);
 
 
 
 
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
Line 1789... Line 1767...
// go_early_tx latched (for proper bit_de_stuff generation)
// go_early_tx latched (for proper bit_de_stuff generation)
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    go_early_tx_latched <= 1'b0;
    go_early_tx_latched <= 1'b0;
//  else if (tx_point_q)
 
  else if (tx_point)
  else if (tx_point)
    go_early_tx_latched <=#Tp 1'b0;
    go_early_tx_latched <=#Tp 1'b0;
  else if (go_early_tx)
  else if (go_early_tx)
    go_early_tx_latched <=#Tp 1'b1;
    go_early_tx_latched <=#Tp 1'b1;
end
end
Line 1826... Line 1803...
begin
begin
  if (rst)
  if (rst)
    transmitter <= 1'b0;
    transmitter <= 1'b0;
  else if (go_tx)
  else if (go_tx)
    transmitter <=#Tp 1'b1;
    transmitter <=#Tp 1'b1;
//  else if ((reset_mode | go_rx_inter ) | ((~tx_state) & tx_state_q))
 
  else if (reset_mode | go_rx_idle)
  else if (reset_mode | go_rx_idle)
    transmitter <=#Tp 1'b0;
    transmitter <=#Tp 1'b0;
end
end
 
 
 
 
Line 1839... Line 1815...
// Node might be both transmitter or receiver (sending error or overload frame)
// Node might be both transmitter or receiver (sending error or overload frame)
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    transmitting <= 1'b0;
    transmitting <= 1'b0;
//  else if (go_error_frame | go_overload_frame | go_tx)
 
  else if (go_error_frame | go_overload_frame | go_tx | send_ack)
  else if (go_error_frame | go_overload_frame | go_tx | send_ack)
    transmitting <=#Tp 1'b1;
    transmitting <=#Tp 1'b1;
  else if (reset_mode | go_rx_idle | (go_rx_id1 & (~tx_state)) | (arbitration_lost & tx_state) | rx_ack_lim)
  else if (reset_mode | go_rx_idle | (go_rx_id1 & (~tx_state)) | (arbitration_lost & tx_state) | rx_ack_lim)
    transmitting <=#Tp 1'b0;
    transmitting <=#Tp 1'b0;
end
end
Line 1853... Line 1828...
begin
begin
  if (rst)
  if (rst)
    suspend <= 1'b0;
    suspend <= 1'b0;
  else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))
  else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))
    suspend <=#Tp 1'b0;
    suspend <=#Tp 1'b0;
//  else if (go_rx_inter & transmitter & node_error_passive)
 
  else if (not_first_bit_of_inter & transmitter & node_error_passive)
  else if (not_first_bit_of_inter & transmitter & node_error_passive)
    suspend <=#Tp 1'b1;
    suspend <=#Tp 1'b1;
end
end
 
 
 
 
Line 1982... Line 1956...
                rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
                rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
//              else if ( (error_flag_over & (~error_flag_over_latched) & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7) & (~rx_err_cnt_blocked)  ) |   // 2
//              else if ( (error_flag_over & (~error_flag_over_latched) & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7) & (~rx_err_cnt_blocked)  ) |   // 2
//              else if ( (error_flag_over & (~error_flag_over_latched) & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7)     ) |   // 2
//              else if ( (error_flag_over & (~error_flag_over_latched) & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7)     ) |   // 2
              else if ( (error_flag_over & (~error_flag_over_latched) & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7)     ) |   // 2
              else if ( (error_flag_over & (~error_flag_over_latched) & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7)     ) |   // 2
                        (go_error_frame & rule5                                                                                  ) |   // 5
                        (go_error_frame & rule5                                                                                  ) |   // 5
//                        (error_frame & sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7)                            )     // 6
 
                        (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7)                            )     // 6
                        (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7)                            )     // 6
                      )
                      )
                rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
                rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
            end
            end
        end
        end
Line 2035... Line 2008...
 
 
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    node_error_passive <= 1'b0;
    node_error_passive <= 1'b0;
//  else if ((rx_err_cnt < 128) & (tx_err_cnt < 9'd128) & error_frame_ended)
 
  else if ((rx_err_cnt < 128) & (tx_err_cnt < 9'd128))
  else if ((rx_err_cnt < 128) & (tx_err_cnt < 9'd128))
    node_error_passive <=#Tp 1'b0;
    node_error_passive <=#Tp 1'b0;
  else if (((rx_err_cnt >= 128) | (tx_err_cnt >= 9'd128)) & (error_frame_ended | go_error_frame | (~reset_mode) & reset_mode_q) & (~node_bus_off))
  else if (((rx_err_cnt >= 128) | (tx_err_cnt >= 9'd128)) & (error_frame_ended | go_error_frame | (~reset_mode) & reset_mode_q) & (~node_bus_off))
    node_error_passive <=#Tp 1'b1;
    node_error_passive <=#Tp 1'b1;
end
end
Line 2107... Line 2079...
  else if ((~reset_mode) & reset_mode_q | node_bus_off_q & (~reset_mode))
  else if ((~reset_mode) & reset_mode_q | node_bus_off_q & (~reset_mode))
    waiting_for_bus_free <=#Tp 1'b1;
    waiting_for_bus_free <=#Tp 1'b1;
end
end
 
 
 
 
assign tx_oen = node_bus_off;
assign bus_off_on = ~node_bus_off;
 
 
assign set_reset_mode = node_bus_off & (~node_bus_off_q);
assign set_reset_mode = node_bus_off & (~node_bus_off_q);
assign error_status = (~reset_mode) & extended_mode? ((rx_err_cnt >= error_warning_limit) | (tx_err_cnt >= error_warning_limit))    :
assign error_status = (~reset_mode) & extended_mode? ((rx_err_cnt >= error_warning_limit) | (tx_err_cnt >= error_warning_limit))    :
                                                     ((rx_err_cnt >= 9'd96) | (tx_err_cnt >= 9'd96))                                      ;
                                                     ((rx_err_cnt >= 9'd96) | (tx_err_cnt >= 9'd96))                                      ;
 
 

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