URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [trunk/] [rtl/] [verilog/] [can_bsp.v] - Diff between revs 141 and 145

Rev 141	Rev 145
Line 48...	Line 48...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.48 2004/05/12 15:58:41 igorm`
	`// Core improved to pass all tests with the Bosch VHDL Reference system.`
	`//`
`// Revision 1.47 2004/02/08 14:24:10 mohor`	`// Revision 1.47 2004/02/08 14:24:10 mohor`
`// Error counters changed.`	`// Error counters changed.`
`//`	`//`
`// Revision 1.46 2003/10/17 05:55:20 markom`	`// Revision 1.46 2003/10/17 05:55:20 markom`
`// mbist signals updated according to newest convention`	`// mbist signals updated according to newest convention`
Line 1884...	Line 1887...
`begin`	`begin`
`if (rst)`	`if (rst)`
`arbitration_lost <= 1'b0;`	`arbitration_lost <= 1'b0;`
`else if (go_rx_idle \| error_frame_ended \| reset_mode)`	`else if (go_rx_idle \| error_frame_ended \| reset_mode)`
`arbitration_lost <=#Tp 1'b0;`	`arbitration_lost <=#Tp 1'b0;`
`else if (transmitter & sample_point & tx & arbitration_field)`	`else if (transmitter & sample_point & tx & arbitration_field & ~sampled_bit)`
`arbitration_lost <=#Tp (~sampled_bit);`	`arbitration_lost <=#Tp 1'b1;`
`end`	`end`


`always @ (posedge clk or posedge rst)`	`always @ (posedge clk or posedge rst)`
`begin`	`begin`