| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.49 2004/10/25 06:37:51 igorm
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// Arbitration bug fixed.
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//
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// Revision 1.48 2004/05/12 15:58:41 igorm
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// Revision 1.48 2004/05/12 15:58:41 igorm
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// Core improved to pass all tests with the Bosch VHDL Reference system.
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// Core improved to pass all tests with the Bosch VHDL Reference system.
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//
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//
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// Revision 1.47 2004/02/08 14:24:10 mohor
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// Revision 1.47 2004/02/08 14:24:10 mohor
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// Error counters changed.
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// Error counters changed.
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| Line 522... |
Line 525... |
reg [2:0] passive_cnt;
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reg [2:0] passive_cnt;
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reg transmitting;
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reg transmitting;
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reg error_frame;
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reg error_frame;
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reg error_frame_q;
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reg enable_error_cnt2;
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reg enable_error_cnt2;
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reg [2:0] error_cnt1;
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reg [2:0] error_cnt1;
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reg [2:0] error_cnt2;
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reg [2:0] error_cnt2;
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reg [2:0] delayed_dominant_cnt;
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reg [2:0] delayed_dominant_cnt;
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reg enable_overload_cnt2;
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reg enable_overload_cnt2;
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| Line 538... |
Line 540... |
reg tx;
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reg tx;
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reg crc_err;
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reg crc_err;
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reg arbitration_lost;
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reg arbitration_lost;
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reg arbitration_lost_q;
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reg arbitration_lost_q;
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reg read_arbitration_lost_capture_reg_q;
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reg [4:0] arbitration_lost_capture;
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reg [4:0] arbitration_lost_capture;
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reg arbitration_cnt_en;
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reg arbitration_cnt_en;
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reg arbitration_blocked;
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reg arbitration_blocked;
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reg tx_q;
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reg tx_q;
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| Line 558... |
Line 561... |
reg transmitter;
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reg transmitter;
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reg finish_msg;
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reg finish_msg;
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reg [8:0] rx_err_cnt;
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reg [8:0] rx_err_cnt;
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reg [8:0] tx_err_cnt;
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reg [8:0] tx_err_cnt;
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reg rx_err_cnt_blocked;
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reg [3:0] bus_free_cnt;
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reg [3:0] bus_free_cnt;
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reg bus_free_cnt_en;
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reg bus_free_cnt_en;
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reg bus_free;
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reg bus_free;
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reg waiting_for_bus_free;
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reg waiting_for_bus_free;
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| Line 573... |
Line 575... |
reg bit_err_latched;
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reg bit_err_latched;
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reg stuff_err_latched;
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reg stuff_err_latched;
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reg form_err_latched;
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reg form_err_latched;
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reg rule3_exc1_1;
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reg rule3_exc1_1;
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reg rule3_exc1_2;
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reg rule3_exc1_2;
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reg rule3_exc2;
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reg suspend;
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reg suspend;
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reg susp_cnt_en;
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reg susp_cnt_en;
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reg [2:0] susp_cnt;
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reg [2:0] susp_cnt;
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reg error_flag_over_latched;
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reg error_flag_over_latched;
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Line 1219... |
else if (rule3_exc1_1 & (error_cnt1 < 3'd7) & sample_point & (~sampled_bit))
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else if (rule3_exc1_1 & (error_cnt1 < 3'd7) & sample_point & (~sampled_bit))
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rule3_exc1_2 <=#Tp 1'b1;
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rule3_exc1_2 <=#Tp 1'b1;
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end
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end
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// Rule 3 exception 2 (Fault confinement).
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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rule3_exc2 <= 1'b0;
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else if (reset_mode | error_flag_over)
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rule3_exc2 <=#Tp 1'b0;
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else if (transmitter & stuff_err & arbitration_field & sample_point & tx & (~sampled_bit))
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rule3_exc2 <=#Tp 1'b1;
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end
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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stuff_err_latched <= 1'b0;
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stuff_err_latched <= 1'b0;
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else if (reset_mode | error_frame_ended | go_overload_frame)
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else if (reset_mode | error_frame_ended | go_overload_frame)
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| Line 1437... |
Line 1425... |
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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error_frame_q <=#Tp 1'b0;
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else if (sample_point)
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error_frame_q <=#Tp error_frame;
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end
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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error_cnt1 <= 3'd0;
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error_cnt1 <= 3'd0;
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else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
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else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
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error_cnt1 <=#Tp 3'd0;
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error_cnt1 <=#Tp 3'd0;
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else if (error_frame & tx_point & (error_cnt1 < 3'd7))
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else if (error_frame & tx_point & (error_cnt1 < 3'd7))
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error_cnt1 <=#Tp error_cnt1 + 1'b1;
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error_cnt1 <=#Tp error_cnt1 + 1'b1;
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| Line 1895... |
Line 1874... |
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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begin
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arbitration_lost_q <=#Tp 1'b0;
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arbitration_lost_q <=#Tp 1'b0;
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read_arbitration_lost_capture_reg_q <=#Tp 1'b0;
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end
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else
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else
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begin
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arbitration_lost_q <=#Tp arbitration_lost;
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arbitration_lost_q <=#Tp arbitration_lost;
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read_arbitration_lost_capture_reg_q <=#Tp read_arbitration_lost_capture_reg;
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end
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end
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end
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assign set_arbitration_lost_irq = arbitration_lost & (~arbitration_lost_q) & (~arbitration_blocked);
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assign set_arbitration_lost_irq = arbitration_lost & (~arbitration_lost_q) & (~arbitration_blocked);
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Line 1916... |
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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arbitration_lost_capture <= 5'h0;
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arbitration_lost_capture <= 5'h0;
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else if (read_arbitration_lost_capture_reg)
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else if (read_arbitration_lost_capture_reg_q)
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arbitration_lost_capture <=#Tp 5'h0;
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arbitration_lost_capture <=#Tp 5'h0;
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else if (sample_point & (~arbitration_blocked) & arbitration_cnt_en & (~bit_de_stuff))
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else if (sample_point & (~arbitration_blocked) & arbitration_cnt_en & (~bit_de_stuff))
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arbitration_lost_capture <=#Tp arbitration_lost_capture + 1'b1;
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arbitration_lost_capture <=#Tp arbitration_lost_capture + 1'b1;
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end
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end
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Line 1987... |
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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rx_err_cnt_blocked <= 1'b0;
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else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
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rx_err_cnt_blocked <=#Tp 1'b0;
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else if (sample_point & (error_cnt1 == 3'd7))
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rx_err_cnt_blocked <=#Tp 1'b1;
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end
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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node_error_passive <= 1'b0;
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node_error_passive <= 1'b0;
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else if ((rx_err_cnt < 128) & (tx_err_cnt < 9'd128))
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else if ((rx_err_cnt < 128) & (tx_err_cnt < 9'd128))
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node_error_passive <=#Tp 1'b0;
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node_error_passive <=#Tp 1'b0;
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else if (((rx_err_cnt >= 128) | (tx_err_cnt >= 9'd128)) & (error_frame_ended | go_error_frame | (~reset_mode) & reset_mode_q) & (~node_bus_off))
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else if (((rx_err_cnt >= 128) | (tx_err_cnt >= 9'd128)) & (error_frame_ended | go_error_frame | (~reset_mode) & reset_mode_q) & (~node_bus_off))
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node_error_passive <=#Tp 1'b1;
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node_error_passive <=#Tp 1'b1;
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