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[/] [can/] [trunk/] [rtl/] [verilog/] [can_bsp.v] - Diff between revs 149 and 151

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Rev 149 Rev 151
Line 48... Line 48...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.50  2004/10/27 18:51:36  igorm
 
// Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
 
//
// Revision 1.49  2004/10/25 06:37:51  igorm
// Revision 1.49  2004/10/25 06:37:51  igorm
// Arbitration bug fixed.
// Arbitration bug fixed.
//
//
// Revision 1.48  2004/05/12 15:58:41  igorm
// Revision 1.48  2004/05/12 15:58:41  igorm
// Core improved to pass all tests with the Bosch VHDL Reference system.
// Core improved to pass all tests with the Bosch VHDL Reference system.
Line 1625... Line 1628...
 
 
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    tx <= 1'b1;
    tx <= 1'b1;
 
  else if (reset_mode)
 
    tx <= 1'b1;
  else if (tx_point)
  else if (tx_point)
    tx <=#Tp tx_next;
    tx <=#Tp tx_next;
end
end
 
 
 
 

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