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[/] [can/] [trunk/] [rtl/] [verilog/] [can_bsp.v] - Diff between revs 149 and 151
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Rev 149 |
Rev 151 |
Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.50 2004/10/27 18:51:36 igorm
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// Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
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//
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// Revision 1.49 2004/10/25 06:37:51 igorm
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// Revision 1.49 2004/10/25 06:37:51 igorm
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// Arbitration bug fixed.
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// Arbitration bug fixed.
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//
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//
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// Revision 1.48 2004/05/12 15:58:41 igorm
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// Revision 1.48 2004/05/12 15:58:41 igorm
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// Core improved to pass all tests with the Bosch VHDL Reference system.
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// Core improved to pass all tests with the Bosch VHDL Reference system.
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Line 1625... |
Line 1628... |
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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tx <= 1'b1;
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tx <= 1'b1;
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else if (reset_mode)
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tx <= 1'b1;
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else if (tx_point)
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else if (tx_point)
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tx <=#Tp tx_next;
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tx <=#Tp tx_next;
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end
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end
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