| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.51 2004/11/15 18:23:21 igorm
|
|
// When CAN was reset by setting the reset_mode signal in mode register, it
|
|
// was possible that CAN was blocked for a short period of time. Problem
|
|
// occured very rarly.
|
|
//
|
// Revision 1.50 2004/10/27 18:51:36 igorm
|
// Revision 1.50 2004/10/27 18:51:36 igorm
|
// Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
|
// Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
|
//
|
//
|
// Revision 1.49 2004/10/25 06:37:51 igorm
|
// Revision 1.49 2004/10/25 06:37:51 igorm
|
// Arbitration bug fixed.
|
// Arbitration bug fixed.
|
| Line 913... |
Line 918... |
// Rx eof state
|
// Rx eof state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_eof <= 1'b0;
|
rx_eof <= 1'b0;
|
else if (go_rx_inter | go_error_frame | go_overload_frame)
|
else if (reset_mode | go_rx_inter | go_error_frame | go_overload_frame)
|
rx_eof <=#Tp 1'b0;
|
rx_eof <=#Tp 1'b0;
|
else if (go_rx_eof)
|
else if (go_rx_eof)
|
rx_eof <=#Tp 1'b1;
|
rx_eof <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 938... |
Line 943... |
// ID register
|
// ID register
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
id <= 29'h0;
|
id <= 29'h0;
|
|
else if (reset_mode)
|
|
id <= 29'h0;
|
else if (sample_point & (rx_id1 | rx_id2) & (~bit_de_stuff))
|
else if (sample_point & (rx_id1 | rx_id2) & (~bit_de_stuff))
|
id <=#Tp {id[27:0], sampled_bit};
|
id <=#Tp {id[27:0], sampled_bit};
|
end
|
end
|
|
|
|
|
// rtr1 bit
|
// rtr1 bit
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rtr1 <= 1'b0;
|
rtr1 <= 1'b0;
|
|
else if (reset_mode)
|
|
rtr1 <= 1'b0;
|
else if (sample_point & rx_rtr1 & (~bit_de_stuff))
|
else if (sample_point & rx_rtr1 & (~bit_de_stuff))
|
rtr1 <=#Tp sampled_bit;
|
rtr1 <=#Tp sampled_bit;
|
end
|
end
|
|
|
|
|
// rtr2 bit
|
// rtr2 bit
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rtr2 <= 1'b0;
|
rtr2 <= 1'b0;
|
|
else if (reset_mode)
|
|
rtr2 <= 1'b0;
|
else if (sample_point & rx_rtr2 & (~bit_de_stuff))
|
else if (sample_point & rx_rtr2 & (~bit_de_stuff))
|
rtr2 <=#Tp sampled_bit;
|
rtr2 <=#Tp sampled_bit;
|
end
|
end
|
|
|
|
|
// ide bit
|
// ide bit
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
ide <= 1'b0;
|
ide <= 1'b0;
|
|
else if (reset_mode)
|
|
ide <= 1'b0;
|
else if (sample_point & rx_ide & (~bit_de_stuff))
|
else if (sample_point & rx_ide & (~bit_de_stuff))
|
ide <=#Tp sampled_bit;
|
ide <=#Tp sampled_bit;
|
end
|
end
|
|
|
|
|
// Data length
|
// Data length
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
data_len <= 4'b0;
|
data_len <= 4'b0;
|
|
else if (reset_mode)
|
|
data_len <= 4'b0;
|
else if (sample_point & rx_dlc & (~bit_de_stuff))
|
else if (sample_point & rx_dlc & (~bit_de_stuff))
|
data_len <=#Tp {data_len[2:0], sampled_bit};
|
data_len <=#Tp {data_len[2:0], sampled_bit};
|
end
|
end
|
|
|
|
|
// Data
|
// Data
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
tmp_data <= 8'h0;
|
tmp_data <= 8'h0;
|
|
else if (reset_mode)
|
|
tmp_data <= 8'h0;
|
else if (sample_point & rx_data & (~bit_de_stuff))
|
else if (sample_point & rx_data & (~bit_de_stuff))
|
tmp_data <=#Tp {tmp_data[6:0], sampled_bit};
|
tmp_data <=#Tp {tmp_data[6:0], sampled_bit};
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
write_data_to_tmp_fifo <= 1'b0;
|
write_data_to_tmp_fifo <= 1'b0;
|
|
else if (reset_mode)
|
|
write_data_to_tmp_fifo <= 1'b0;
|
else if (sample_point & rx_data & (~bit_de_stuff) & (&bit_cnt[2:0]))
|
else if (sample_point & rx_data & (~bit_de_stuff) & (&bit_cnt[2:0]))
|
write_data_to_tmp_fifo <=#Tp 1'b1;
|
write_data_to_tmp_fifo <=#Tp 1'b1;
|
else
|
else
|
write_data_to_tmp_fifo <=#Tp 1'b0;
|
write_data_to_tmp_fifo <=#Tp 1'b0;
|
end
|
end
|
| Line 1008... |
Line 1027... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
byte_cnt <= 3'h0;
|
byte_cnt <= 3'h0;
|
|
else if (reset_mode)
|
|
byte_cnt <= 3'h0;
|
else if (write_data_to_tmp_fifo)
|
else if (write_data_to_tmp_fifo)
|
byte_cnt <=#Tp byte_cnt + 1'b1;
|
byte_cnt <=#Tp byte_cnt + 1'b1;
|
else if (reset_mode | (sample_point & go_rx_crc_lim))
|
else if (sample_point & go_rx_crc_lim)
|
byte_cnt <=#Tp 3'h0;
|
byte_cnt <=#Tp 3'h0;
|
end
|
end
|
|
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
| Line 1028... |
Line 1049... |
// CRC
|
// CRC
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
crc_in <= 15'h0;
|
crc_in <= 15'h0;
|
|
else if (reset_mode)
|
|
crc_in <= 15'h0;
|
else if (sample_point & rx_crc & (~bit_de_stuff))
|
else if (sample_point & rx_crc & (~bit_de_stuff))
|
crc_in <=#Tp {crc_in[13:0], sampled_bit};
|
crc_in <=#Tp {crc_in[13:0], sampled_bit};
|
end
|
end
|
|
|
|
|
// bit_cnt
|
// bit_cnt
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bit_cnt <= 6'd0;
|
bit_cnt <= 6'd0;
|
|
else if (reset_mode)
|
|
bit_cnt <= 6'd0;
|
else if (go_rx_id1 | go_rx_id2 | go_rx_dlc | go_rx_data | go_rx_crc |
|
else if (go_rx_id1 | go_rx_id2 | go_rx_dlc | go_rx_data | go_rx_crc |
|
go_rx_ack | go_rx_eof | go_rx_inter | go_error_frame | go_overload_frame)
|
go_rx_ack | go_rx_eof | go_rx_inter | go_error_frame | go_overload_frame)
|
bit_cnt <=#Tp 6'd0;
|
bit_cnt <=#Tp 6'd0;
|
else if (sample_point & (~bit_de_stuff))
|
else if (sample_point & (~bit_de_stuff))
|
bit_cnt <=#Tp bit_cnt + 1'b1;
|
bit_cnt <=#Tp bit_cnt + 1'b1;
|
| Line 1051... |
Line 1076... |
// eof_cnt
|
// eof_cnt
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
eof_cnt <= 3'd0;
|
eof_cnt <= 3'd0;
|
|
else if (reset_mode)
|
|
eof_cnt <= 3'd0;
|
else if (sample_point)
|
else if (sample_point)
|
begin
|
begin
|
if (reset_mode | go_rx_inter | go_error_frame | go_overload_frame)
|
if (go_rx_inter | go_error_frame | go_overload_frame)
|
eof_cnt <=#Tp 3'd0;
|
eof_cnt <=#Tp 3'd0;
|
else if (rx_eof)
|
else if (rx_eof)
|
eof_cnt <=#Tp eof_cnt + 1'b1;
|
eof_cnt <=#Tp eof_cnt + 1'b1;
|
end
|
end
|
end
|
end
|
| Line 1066... |
Line 1093... |
// Enabling bit de-stuffing
|
// Enabling bit de-stuffing
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bit_stuff_cnt_en <= 1'b0;
|
bit_stuff_cnt_en <= 1'b0;
|
|
else if (reset_mode)
|
|
bit_stuff_cnt_en <= 1'b0;
|
else if (bit_de_stuff_set)
|
else if (bit_de_stuff_set)
|
bit_stuff_cnt_en <=#Tp 1'b1;
|
bit_stuff_cnt_en <=#Tp 1'b1;
|
else if (bit_de_stuff_reset)
|
else if (bit_de_stuff_reset)
|
bit_stuff_cnt_en <=#Tp 1'b0;
|
bit_stuff_cnt_en <=#Tp 1'b0;
|
end
|
end
|
| Line 1078... |
Line 1107... |
// bit_stuff_cnt
|
// bit_stuff_cnt
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bit_stuff_cnt <= 3'h1;
|
bit_stuff_cnt <= 3'h1;
|
|
else if (reset_mode)
|
|
bit_stuff_cnt <= 3'h1;
|
else if (bit_de_stuff_reset)
|
else if (bit_de_stuff_reset)
|
bit_stuff_cnt <=#Tp 3'h1;
|
bit_stuff_cnt <=#Tp 3'h1;
|
else if (sample_point & bit_stuff_cnt_en)
|
else if (sample_point & bit_stuff_cnt_en)
|
begin
|
begin
|
if (bit_stuff_cnt == 3'h5)
|
if (bit_stuff_cnt == 3'h5)
|
| Line 1097... |
Line 1128... |
// bit_stuff_cnt_tx
|
// bit_stuff_cnt_tx
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bit_stuff_cnt_tx <= 3'h1;
|
bit_stuff_cnt_tx <= 3'h1;
|
|
else if (reset_mode)
|
|
bit_stuff_cnt_tx <= 3'h1;
|
else if (bit_de_stuff_reset)
|
else if (bit_de_stuff_reset)
|
bit_stuff_cnt_tx <=#Tp 3'h1;
|
bit_stuff_cnt_tx <=#Tp 3'h1;
|
else if (tx_point_q & bit_stuff_cnt_en)
|
else if (tx_point_q & bit_stuff_cnt_en)
|
begin
|
begin
|
if (bit_stuff_cnt_tx == 3'h5)
|
if (bit_stuff_cnt_tx == 3'h5)
|
| Line 1142... |
Line 1175... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
crc_enable <= 1'b0;
|
crc_enable <= 1'b0;
|
else if (go_crc_enable)
|
|
crc_enable <=#Tp 1'b1;
|
|
else if (reset_mode | rst_crc_enable)
|
else if (reset_mode | rst_crc_enable)
|
crc_enable <=#Tp 1'b0;
|
crc_enable <=#Tp 1'b0;
|
|
else if (go_crc_enable)
|
|
crc_enable <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// CRC error generation
|
// CRC error generation
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
crc_err <= 1'b0;
|
crc_err <= 1'b0;
|
else if (go_rx_ack)
|
|
crc_err <=#Tp crc_in != calculated_crc;
|
|
else if (reset_mode | error_frame_ended)
|
else if (reset_mode | error_frame_ended)
|
crc_err <=#Tp 1'b0;
|
crc_err <=#Tp 1'b0;
|
|
else if (go_rx_ack)
|
|
crc_err <=#Tp crc_in != calculated_crc;
|
end
|
end
|
|
|
|
|
// Conditions for form error
|
// Conditions for form error
|
assign form_err = sample_point & ( ((~bit_de_stuff) & rx_crc_lim & (~sampled_bit) ) |
|
assign form_err = sample_point & ( ((~bit_de_stuff) & rx_crc_lim & (~sampled_bit) ) |
|
| Line 1639... |
Line 1672... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
tx_q <=#Tp 1'b0;
|
tx_q <=#Tp 1'b0;
|
|
else if (reset_mode)
|
|
tx_q <=#Tp 1'b0;
|
else if (tx_point)
|
else if (tx_point)
|
tx_q <=#Tp tx & (~go_early_tx_latched);
|
tx_q <=#Tp tx & (~go_early_tx_latched);
|
end
|
end
|
|
|
|
|
/* Delayed tx point */
|
/* Delayed tx point */
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
tx_point_q <=#Tp 1'b0;
|
tx_point_q <=#Tp 1'b0;
|
|
else if (reset_mode)
|
|
tx_point_q <=#Tp 1'b0;
|
else
|
else
|
tx_point_q <=#Tp tx_point;
|
tx_point_q <=#Tp tx_point;
|
end
|
end
|
|
|
|
|
| Line 1766... |
Line 1803... |
// go_early_tx latched (for proper bit_de_stuff generation)
|
// go_early_tx latched (for proper bit_de_stuff generation)
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
go_early_tx_latched <= 1'b0;
|
go_early_tx_latched <= 1'b0;
|
else if (tx_point)
|
else if (reset_mode || tx_point)
|
go_early_tx_latched <=#Tp 1'b0;
|
go_early_tx_latched <=#Tp 1'b0;
|
else if (go_early_tx)
|
else if (go_early_tx)
|
go_early_tx_latched <=#Tp 1'b1;
|
go_early_tx_latched <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 1789... |
Line 1826... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
tx_state_q <=#Tp 1'b0;
|
tx_state_q <=#Tp 1'b0;
|
|
else if (reset_mode)
|
|
tx_state_q <=#Tp 1'b0;
|
else
|
else
|
tx_state_q <=#Tp tx_state;
|
tx_state_q <=#Tp tx_state;
|
end
|
end
|
|
|
|
|
| Line 1883... |
Line 1922... |
if (rst)
|
if (rst)
|
begin
|
begin
|
arbitration_lost_q <=#Tp 1'b0;
|
arbitration_lost_q <=#Tp 1'b0;
|
read_arbitration_lost_capture_reg_q <=#Tp 1'b0;
|
read_arbitration_lost_capture_reg_q <=#Tp 1'b0;
|
end
|
end
|
|
else if (reset_mode)
|
|
begin
|
|
arbitration_lost_q <=#Tp 1'b0;
|
|
read_arbitration_lost_capture_reg_q <=#Tp 1'b0;
|
|
end
|
else
|
else
|
begin
|
begin
|
arbitration_lost_q <=#Tp arbitration_lost;
|
arbitration_lost_q <=#Tp arbitration_lost;
|
read_arbitration_lost_capture_reg_q <=#Tp read_arbitration_lost_capture_reg;
|
read_arbitration_lost_capture_reg_q <=#Tp read_arbitration_lost_capture_reg;
|
end
|
end
|
| Line 1898... |
Line 1942... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
arbitration_cnt_en <= 1'b0;
|
arbitration_cnt_en <= 1'b0;
|
else if (arbitration_blocked)
|
else if (reset_mode || arbitration_blocked)
|
arbitration_cnt_en <=#Tp 1'b0;
|
arbitration_cnt_en <=#Tp 1'b0;
|
else if (rx_id1 & sample_point & (~arbitration_blocked))
|
else if (rx_id1 & sample_point & (~arbitration_blocked))
|
arbitration_cnt_en <=#Tp 1'b1;
|
arbitration_cnt_en <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 1910... |
Line 1954... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
arbitration_blocked <= 1'b0;
|
arbitration_blocked <= 1'b0;
|
else if (read_arbitration_lost_capture_reg)
|
else if (reset_mode || read_arbitration_lost_capture_reg)
|
arbitration_blocked <=#Tp 1'b0;
|
arbitration_blocked <=#Tp 1'b0;
|
else if (set_arbitration_lost_irq)
|
else if (set_arbitration_lost_irq)
|
arbitration_blocked <=#Tp 1'b1;
|
arbitration_blocked <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 2046... |
Line 2090... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bus_free <= 1'b0;
|
bus_free <= 1'b0;
|
|
else if (reset_mode)
|
|
bus_free <= 1'b0;
|
else if (sample_point & sampled_bit & (bus_free_cnt==4'd10))
|
else if (sample_point & sampled_bit & (bus_free_cnt==4'd10))
|
bus_free <=#Tp 1'b1;
|
bus_free <=#Tp 1'b1;
|
else
|
else
|
bus_free <=#Tp 1'b0;
|
bus_free <=#Tp 1'b0;
|
end
|
end
|
| Line 2057... |
Line 2103... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
waiting_for_bus_free <= 1'b1;
|
waiting_for_bus_free <= 1'b1;
|
|
else if (reset_mode)
|
|
waiting_for_bus_free <= 1'b1;
|
else if (bus_free & (~node_bus_off))
|
else if (bus_free & (~node_bus_off))
|
waiting_for_bus_free <=#Tp 1'b0;
|
waiting_for_bus_free <=#Tp 1'b0;
|
else if ((~reset_mode) & reset_mode_q | node_bus_off_q & (~reset_mode))
|
else if ((~reset_mode) & reset_mode_q | node_bus_off_q & (~reset_mode))
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waiting_for_bus_free <=#Tp 1'b1;
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waiting_for_bus_free <=#Tp 1'b1;
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end
|
end
|
|
|
|
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assign bus_off_on = ~node_bus_off;
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assign bus_off_on = ~node_bus_off;
|
|
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assign set_reset_mode = node_bus_off & (~node_bus_off_q);
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assign set_reset_mode = node_bus_off & (~node_bus_off_q);
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assign error_status = (~reset_mode) & extended_mode? ((rx_err_cnt >= error_warning_limit) | (tx_err_cnt >= error_warning_limit)) :
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assign error_status = extended_mode? ((rx_err_cnt >= error_warning_limit) | (tx_err_cnt >= error_warning_limit)) :
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((rx_err_cnt >= 9'd96) | (tx_err_cnt >= 9'd96)) ;
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((rx_err_cnt >= 9'd96) | (tx_err_cnt >= 9'd96)) ;
|
|
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assign transmit_status = transmitting | (extended_mode & waiting_for_bus_free);
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assign transmit_status = transmitting || (extended_mode && waiting_for_bus_free);
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assign receive_status = (~rx_idle) & (~transmitting) | (extended_mode & waiting_for_bus_free);
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assign receive_status = extended_mode ? (waiting_for_bus_free || (!rx_idle) && (!transmitting)) :
|
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((!waiting_for_bus_free) && (!rx_idle) && (!transmitting));
|
|
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/* Error code capture register */
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/* Error code capture register */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
