| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.52 2004/11/18 12:39:21 igorm
|
|
// Fixes for compatibility after the SW reset.
|
|
//
|
// Revision 1.51 2004/11/15 18:23:21 igorm
|
// Revision 1.51 2004/11/15 18:23:21 igorm
|
// When CAN was reset by setting the reset_mode signal in mode register, it
|
// When CAN was reset by setting the reset_mode signal in mode register, it
|
// was possible that CAN was blocked for a short period of time. Problem
|
// was possible that CAN was blocked for a short period of time. Problem
|
// occured very rarly.
|
// occured very rarly.
|
//
|
//
|
| Line 548... |
Line 551... |
reg tx;
|
reg tx;
|
reg crc_err;
|
reg crc_err;
|
|
|
reg arbitration_lost;
|
reg arbitration_lost;
|
reg arbitration_lost_q;
|
reg arbitration_lost_q;
|
reg read_arbitration_lost_capture_reg_q;
|
reg arbitration_field_d;
|
reg [4:0] arbitration_lost_capture;
|
reg [4:0] arbitration_lost_capture;
|
reg arbitration_cnt_en;
|
reg [4:0] arbitration_cnt;
|
reg arbitration_blocked;
|
reg arbitration_blocked;
|
reg tx_q;
|
reg tx_q;
|
|
|
reg need_to_tx; // When the CAN core has something to transmit and a dominant bit is sampled at the third bit
|
reg need_to_tx; // When the CAN core has something to transmit and a dominant bit is sampled at the third bit
|
reg [3:0] data_cnt; // Counting the data bytes that are written to FIFO
|
reg [3:0] data_cnt; // Counting the data bytes that are written to FIFO
|
| Line 725... |
Line 728... |
|
|
assign go_crc_enable = hard_sync | go_tx;
|
assign go_crc_enable = hard_sync | go_tx;
|
assign rst_crc_enable = go_rx_crc;
|
assign rst_crc_enable = go_rx_crc;
|
|
|
assign bit_de_stuff_set = go_rx_id1 & (~go_error_frame);
|
assign bit_de_stuff_set = go_rx_id1 & (~go_error_frame);
|
assign bit_de_stuff_reset = go_rx_ack | reset_mode | go_error_frame | go_overload_frame;
|
assign bit_de_stuff_reset = go_rx_ack | go_error_frame | go_overload_frame;
|
|
|
assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
|
assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
|
assign limited_data_len = (data_len < 4'h8)? data_len : 4'h8;
|
assign limited_data_len = (data_len < 4'h8)? data_len : 4'h8;
|
|
|
assign ack_err = rx_ack & sample_point & sampled_bit & tx_state & (~self_test_mode);
|
assign ack_err = rx_ack & sample_point & sampled_bit & tx_state & (~self_test_mode);
|
assign bit_err = (tx_state | error_frame | overload_frame | rx_ack) & sample_point & (tx != sampled_bit) & (~bit_err_exc1) & (~bit_err_exc2) & (~bit_err_exc3) & (~bit_err_exc4) & (~bit_err_exc5) & (~bit_err_exc6);
|
assign bit_err = (tx_state | error_frame | overload_frame | rx_ack) & sample_point & (tx != sampled_bit) & (~bit_err_exc1) & (~bit_err_exc2) & (~bit_err_exc3) & (~bit_err_exc4) & (~bit_err_exc5) & (~bit_err_exc6) & (~reset_mode);
|
assign bit_err_exc1 = tx_state & arbitration_field & tx;
|
assign bit_err_exc1 = tx_state & arbitration_field & tx;
|
assign bit_err_exc2 = rx_ack & tx;
|
assign bit_err_exc2 = rx_ack & tx;
|
assign bit_err_exc3 = error_frame & node_error_passive & (error_cnt1 < 3'd7);
|
assign bit_err_exc3 = error_frame & node_error_passive & (error_cnt1 < 3'd7);
|
assign bit_err_exc4 = (error_frame & (error_cnt1 == 3'd7) & (~enable_error_cnt2)) | (overload_frame & (overload_cnt1 == 3'd7) & (~enable_overload_cnt2));
|
assign bit_err_exc4 = (error_frame & (error_cnt1 == 3'd7) & (~enable_error_cnt2)) | (overload_frame & (overload_cnt1 == 3'd7) & (~enable_overload_cnt2));
|
assign bit_err_exc5 = (error_frame & (error_cnt2 == 3'd7)) | (overload_frame & (overload_cnt2 == 3'd7));
|
assign bit_err_exc5 = (error_frame & (error_cnt2 == 3'd7)) | (overload_frame & (overload_cnt2 == 3'd7));
|
| Line 750... |
Line 753... |
// Rx idle state
|
// Rx idle state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_idle <= 1'b0;
|
rx_idle <= 1'b0;
|
else if (reset_mode | go_rx_id1 | go_error_frame)
|
else if (go_rx_id1 | go_error_frame)
|
rx_idle <=#Tp 1'b0;
|
rx_idle <=#Tp 1'b0;
|
else if (go_rx_idle)
|
else if (go_rx_idle)
|
rx_idle <=#Tp 1'b1;
|
rx_idle <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 762... |
Line 765... |
// Rx id1 state
|
// Rx id1 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_id1 <= 1'b0;
|
rx_id1 <= 1'b0;
|
else if (reset_mode | go_rx_rtr1 | go_error_frame)
|
else if (go_rx_rtr1 | go_error_frame)
|
rx_id1 <=#Tp 1'b0;
|
rx_id1 <=#Tp 1'b0;
|
else if (go_rx_id1)
|
else if (go_rx_id1)
|
rx_id1 <=#Tp 1'b1;
|
rx_id1 <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 774... |
Line 777... |
// Rx rtr1 state
|
// Rx rtr1 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_rtr1 <= 1'b0;
|
rx_rtr1 <= 1'b0;
|
else if (reset_mode | go_rx_ide | go_error_frame)
|
else if (go_rx_ide | go_error_frame)
|
rx_rtr1 <=#Tp 1'b0;
|
rx_rtr1 <=#Tp 1'b0;
|
else if (go_rx_rtr1)
|
else if (go_rx_rtr1)
|
rx_rtr1 <=#Tp 1'b1;
|
rx_rtr1 <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 786... |
Line 789... |
// Rx ide state
|
// Rx ide state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_ide <= 1'b0;
|
rx_ide <= 1'b0;
|
else if (reset_mode | go_rx_r0 | go_rx_id2 | go_error_frame)
|
else if (go_rx_r0 | go_rx_id2 | go_error_frame)
|
rx_ide <=#Tp 1'b0;
|
rx_ide <=#Tp 1'b0;
|
else if (go_rx_ide)
|
else if (go_rx_ide)
|
rx_ide <=#Tp 1'b1;
|
rx_ide <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 798... |
Line 801... |
// Rx id2 state
|
// Rx id2 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_id2 <= 1'b0;
|
rx_id2 <= 1'b0;
|
else if (reset_mode | go_rx_rtr2 | go_error_frame)
|
else if (go_rx_rtr2 | go_error_frame)
|
rx_id2 <=#Tp 1'b0;
|
rx_id2 <=#Tp 1'b0;
|
else if (go_rx_id2)
|
else if (go_rx_id2)
|
rx_id2 <=#Tp 1'b1;
|
rx_id2 <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 810... |
Line 813... |
// Rx rtr2 state
|
// Rx rtr2 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_rtr2 <= 1'b0;
|
rx_rtr2 <= 1'b0;
|
else if (reset_mode | go_rx_r1 | go_error_frame)
|
else if (go_rx_r1 | go_error_frame)
|
rx_rtr2 <=#Tp 1'b0;
|
rx_rtr2 <=#Tp 1'b0;
|
else if (go_rx_rtr2)
|
else if (go_rx_rtr2)
|
rx_rtr2 <=#Tp 1'b1;
|
rx_rtr2 <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 822... |
Line 825... |
// Rx r0 state
|
// Rx r0 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_r1 <= 1'b0;
|
rx_r1 <= 1'b0;
|
else if (reset_mode | go_rx_r0 | go_error_frame)
|
else if (go_rx_r0 | go_error_frame)
|
rx_r1 <=#Tp 1'b0;
|
rx_r1 <=#Tp 1'b0;
|
else if (go_rx_r1)
|
else if (go_rx_r1)
|
rx_r1 <=#Tp 1'b1;
|
rx_r1 <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 834... |
Line 837... |
// Rx r0 state
|
// Rx r0 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_r0 <= 1'b0;
|
rx_r0 <= 1'b0;
|
else if (reset_mode | go_rx_dlc | go_error_frame)
|
else if (go_rx_dlc | go_error_frame)
|
rx_r0 <=#Tp 1'b0;
|
rx_r0 <=#Tp 1'b0;
|
else if (go_rx_r0)
|
else if (go_rx_r0)
|
rx_r0 <=#Tp 1'b1;
|
rx_r0 <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 846... |
Line 849... |
// Rx dlc state
|
// Rx dlc state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_dlc <= 1'b0;
|
rx_dlc <= 1'b0;
|
else if (reset_mode | go_rx_data | go_rx_crc | go_error_frame)
|
else if (go_rx_data | go_rx_crc | go_error_frame)
|
rx_dlc <=#Tp 1'b0;
|
rx_dlc <=#Tp 1'b0;
|
else if (go_rx_dlc)
|
else if (go_rx_dlc)
|
rx_dlc <=#Tp 1'b1;
|
rx_dlc <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 858... |
Line 861... |
// Rx data state
|
// Rx data state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_data <= 1'b0;
|
rx_data <= 1'b0;
|
else if (reset_mode | go_rx_crc | go_error_frame)
|
else if (go_rx_crc | go_error_frame)
|
rx_data <=#Tp 1'b0;
|
rx_data <=#Tp 1'b0;
|
else if (go_rx_data)
|
else if (go_rx_data)
|
rx_data <=#Tp 1'b1;
|
rx_data <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 870... |
Line 873... |
// Rx crc state
|
// Rx crc state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_crc <= 1'b0;
|
rx_crc <= 1'b0;
|
else if (reset_mode | go_rx_crc_lim | go_error_frame)
|
else if (go_rx_crc_lim | go_error_frame)
|
rx_crc <=#Tp 1'b0;
|
rx_crc <=#Tp 1'b0;
|
else if (go_rx_crc)
|
else if (go_rx_crc)
|
rx_crc <=#Tp 1'b1;
|
rx_crc <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 882... |
Line 885... |
// Rx crc delimiter state
|
// Rx crc delimiter state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_crc_lim <= 1'b0;
|
rx_crc_lim <= 1'b0;
|
else if (reset_mode | go_rx_ack | go_error_frame)
|
else if (go_rx_ack | go_error_frame)
|
rx_crc_lim <=#Tp 1'b0;
|
rx_crc_lim <=#Tp 1'b0;
|
else if (go_rx_crc_lim)
|
else if (go_rx_crc_lim)
|
rx_crc_lim <=#Tp 1'b1;
|
rx_crc_lim <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 894... |
Line 897... |
// Rx ack state
|
// Rx ack state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_ack <= 1'b0;
|
rx_ack <= 1'b0;
|
else if (reset_mode | go_rx_ack_lim | go_error_frame)
|
else if (go_rx_ack_lim | go_error_frame)
|
rx_ack <=#Tp 1'b0;
|
rx_ack <=#Tp 1'b0;
|
else if (go_rx_ack)
|
else if (go_rx_ack)
|
rx_ack <=#Tp 1'b1;
|
rx_ack <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 906... |
Line 909... |
// Rx ack delimiter state
|
// Rx ack delimiter state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_ack_lim <= 1'b0;
|
rx_ack_lim <= 1'b0;
|
else if (reset_mode | go_rx_eof | go_error_frame)
|
else if (go_rx_eof | go_error_frame)
|
rx_ack_lim <=#Tp 1'b0;
|
rx_ack_lim <=#Tp 1'b0;
|
else if (go_rx_ack_lim)
|
else if (go_rx_ack_lim)
|
rx_ack_lim <=#Tp 1'b1;
|
rx_ack_lim <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 918... |
Line 921... |
// Rx eof state
|
// Rx eof state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_eof <= 1'b0;
|
rx_eof <= 1'b0;
|
else if (reset_mode | go_rx_inter | go_error_frame | go_overload_frame)
|
else if (go_rx_inter | go_error_frame | go_overload_frame)
|
rx_eof <=#Tp 1'b0;
|
rx_eof <=#Tp 1'b0;
|
else if (go_rx_eof)
|
else if (go_rx_eof)
|
rx_eof <=#Tp 1'b1;
|
rx_eof <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 931... |
Line 934... |
// Interframe space
|
// Interframe space
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_inter <= 1'b0;
|
rx_inter <= 1'b0;
|
else if (reset_mode | go_rx_idle | go_rx_id1 | go_overload_frame | go_error_frame)
|
else if (go_rx_idle | go_rx_id1 | go_overload_frame | go_error_frame)
|
rx_inter <=#Tp 1'b0;
|
rx_inter <=#Tp 1'b0;
|
else if (go_rx_inter)
|
else if (go_rx_inter)
|
rx_inter <=#Tp 1'b1;
|
rx_inter <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 943... |
Line 946... |
// ID register
|
// ID register
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
id <= 29'h0;
|
id <= 29'h0;
|
else if (reset_mode)
|
|
id <= 29'h0;
|
|
else if (sample_point & (rx_id1 | rx_id2) & (~bit_de_stuff))
|
else if (sample_point & (rx_id1 | rx_id2) & (~bit_de_stuff))
|
id <=#Tp {id[27:0], sampled_bit};
|
id <=#Tp {id[27:0], sampled_bit};
|
end
|
end
|
|
|
|
|
// rtr1 bit
|
// rtr1 bit
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rtr1 <= 1'b0;
|
rtr1 <= 1'b0;
|
else if (reset_mode)
|
|
rtr1 <= 1'b0;
|
|
else if (sample_point & rx_rtr1 & (~bit_de_stuff))
|
else if (sample_point & rx_rtr1 & (~bit_de_stuff))
|
rtr1 <=#Tp sampled_bit;
|
rtr1 <=#Tp sampled_bit;
|
end
|
end
|
|
|
|
|
// rtr2 bit
|
// rtr2 bit
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rtr2 <= 1'b0;
|
rtr2 <= 1'b0;
|
else if (reset_mode)
|
|
rtr2 <= 1'b0;
|
|
else if (sample_point & rx_rtr2 & (~bit_de_stuff))
|
else if (sample_point & rx_rtr2 & (~bit_de_stuff))
|
rtr2 <=#Tp sampled_bit;
|
rtr2 <=#Tp sampled_bit;
|
end
|
end
|
|
|
|
|
// ide bit
|
// ide bit
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
ide <= 1'b0;
|
ide <= 1'b0;
|
else if (reset_mode)
|
|
ide <= 1'b0;
|
|
else if (sample_point & rx_ide & (~bit_de_stuff))
|
else if (sample_point & rx_ide & (~bit_de_stuff))
|
ide <=#Tp sampled_bit;
|
ide <=#Tp sampled_bit;
|
end
|
end
|
|
|
|
|
// Data length
|
// Data length
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
data_len <= 4'b0;
|
data_len <= 4'b0;
|
else if (reset_mode)
|
|
data_len <= 4'b0;
|
|
else if (sample_point & rx_dlc & (~bit_de_stuff))
|
else if (sample_point & rx_dlc & (~bit_de_stuff))
|
data_len <=#Tp {data_len[2:0], sampled_bit};
|
data_len <=#Tp {data_len[2:0], sampled_bit};
|
end
|
end
|
|
|
|
|
// Data
|
// Data
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
tmp_data <= 8'h0;
|
tmp_data <= 8'h0;
|
else if (reset_mode)
|
|
tmp_data <= 8'h0;
|
|
else if (sample_point & rx_data & (~bit_de_stuff))
|
else if (sample_point & rx_data & (~bit_de_stuff))
|
tmp_data <=#Tp {tmp_data[6:0], sampled_bit};
|
tmp_data <=#Tp {tmp_data[6:0], sampled_bit};
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
write_data_to_tmp_fifo <= 1'b0;
|
write_data_to_tmp_fifo <= 1'b0;
|
else if (reset_mode)
|
|
write_data_to_tmp_fifo <= 1'b0;
|
|
else if (sample_point & rx_data & (~bit_de_stuff) & (&bit_cnt[2:0]))
|
else if (sample_point & rx_data & (~bit_de_stuff) & (&bit_cnt[2:0]))
|
write_data_to_tmp_fifo <=#Tp 1'b1;
|
write_data_to_tmp_fifo <=#Tp 1'b1;
|
else
|
else
|
write_data_to_tmp_fifo <=#Tp 1'b0;
|
write_data_to_tmp_fifo <=#Tp 1'b0;
|
end
|
end
|
| Line 1027... |
Line 1016... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
byte_cnt <= 3'h0;
|
byte_cnt <= 3'h0;
|
else if (reset_mode)
|
|
byte_cnt <= 3'h0;
|
|
else if (write_data_to_tmp_fifo)
|
else if (write_data_to_tmp_fifo)
|
byte_cnt <=#Tp byte_cnt + 1'b1;
|
byte_cnt <=#Tp byte_cnt + 1'b1;
|
else if (sample_point & go_rx_crc_lim)
|
else if (sample_point & go_rx_crc_lim)
|
byte_cnt <=#Tp 3'h0;
|
byte_cnt <=#Tp 3'h0;
|
end
|
end
|
| Line 1049... |
Line 1036... |
// CRC
|
// CRC
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
crc_in <= 15'h0;
|
crc_in <= 15'h0;
|
else if (reset_mode)
|
|
crc_in <= 15'h0;
|
|
else if (sample_point & rx_crc & (~bit_de_stuff))
|
else if (sample_point & rx_crc & (~bit_de_stuff))
|
crc_in <=#Tp {crc_in[13:0], sampled_bit};
|
crc_in <=#Tp {crc_in[13:0], sampled_bit};
|
end
|
end
|
|
|
|
|
// bit_cnt
|
// bit_cnt
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bit_cnt <= 6'd0;
|
bit_cnt <= 6'd0;
|
else if (reset_mode)
|
|
bit_cnt <= 6'd0;
|
|
else if (go_rx_id1 | go_rx_id2 | go_rx_dlc | go_rx_data | go_rx_crc |
|
else if (go_rx_id1 | go_rx_id2 | go_rx_dlc | go_rx_data | go_rx_crc |
|
go_rx_ack | go_rx_eof | go_rx_inter | go_error_frame | go_overload_frame)
|
go_rx_ack | go_rx_eof | go_rx_inter | go_error_frame | go_overload_frame)
|
bit_cnt <=#Tp 6'd0;
|
bit_cnt <=#Tp 6'd0;
|
else if (sample_point & (~bit_de_stuff))
|
else if (sample_point & (~bit_de_stuff))
|
bit_cnt <=#Tp bit_cnt + 1'b1;
|
bit_cnt <=#Tp bit_cnt + 1'b1;
|
| Line 1076... |
Line 1059... |
// eof_cnt
|
// eof_cnt
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
eof_cnt <= 3'd0;
|
eof_cnt <= 3'd0;
|
else if (reset_mode)
|
|
eof_cnt <= 3'd0;
|
|
else if (sample_point)
|
else if (sample_point)
|
begin
|
begin
|
if (go_rx_inter | go_error_frame | go_overload_frame)
|
if (go_rx_inter | go_error_frame | go_overload_frame)
|
eof_cnt <=#Tp 3'd0;
|
eof_cnt <=#Tp 3'd0;
|
else if (rx_eof)
|
else if (rx_eof)
|
| Line 1093... |
Line 1074... |
// Enabling bit de-stuffing
|
// Enabling bit de-stuffing
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bit_stuff_cnt_en <= 1'b0;
|
bit_stuff_cnt_en <= 1'b0;
|
else if (reset_mode)
|
|
bit_stuff_cnt_en <= 1'b0;
|
|
else if (bit_de_stuff_set)
|
else if (bit_de_stuff_set)
|
bit_stuff_cnt_en <=#Tp 1'b1;
|
bit_stuff_cnt_en <=#Tp 1'b1;
|
else if (bit_de_stuff_reset)
|
else if (bit_de_stuff_reset)
|
bit_stuff_cnt_en <=#Tp 1'b0;
|
bit_stuff_cnt_en <=#Tp 1'b0;
|
end
|
end
|
| Line 1107... |
Line 1086... |
// bit_stuff_cnt
|
// bit_stuff_cnt
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bit_stuff_cnt <= 3'h1;
|
bit_stuff_cnt <= 3'h1;
|
else if (reset_mode)
|
|
bit_stuff_cnt <= 3'h1;
|
|
else if (bit_de_stuff_reset)
|
else if (bit_de_stuff_reset)
|
bit_stuff_cnt <=#Tp 3'h1;
|
bit_stuff_cnt <=#Tp 3'h1;
|
else if (sample_point & bit_stuff_cnt_en)
|
else if (sample_point & bit_stuff_cnt_en)
|
begin
|
begin
|
if (bit_stuff_cnt == 3'h5)
|
if (bit_stuff_cnt == 3'h5)
|
| Line 1128... |
Line 1105... |
// bit_stuff_cnt_tx
|
// bit_stuff_cnt_tx
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bit_stuff_cnt_tx <= 3'h1;
|
bit_stuff_cnt_tx <= 3'h1;
|
else if (reset_mode)
|
else if (reset_mode || bit_de_stuff_reset)
|
bit_stuff_cnt_tx <= 3'h1;
|
|
else if (bit_de_stuff_reset)
|
|
bit_stuff_cnt_tx <=#Tp 3'h1;
|
bit_stuff_cnt_tx <=#Tp 3'h1;
|
else if (tx_point_q & bit_stuff_cnt_en)
|
else if (tx_point_q & bit_stuff_cnt_en)
|
begin
|
begin
|
if (bit_stuff_cnt_tx == 3'h5)
|
if (bit_stuff_cnt_tx == 3'h5)
|
bit_stuff_cnt_tx <=#Tp 3'h1;
|
bit_stuff_cnt_tx <=#Tp 3'h1;
|
| Line 1175... |
Line 1150... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
crc_enable <= 1'b0;
|
crc_enable <= 1'b0;
|
else if (reset_mode | rst_crc_enable)
|
else if (rst_crc_enable)
|
crc_enable <=#Tp 1'b0;
|
crc_enable <=#Tp 1'b0;
|
else if (go_crc_enable)
|
else if (go_crc_enable)
|
crc_enable <=#Tp 1'b1;
|
crc_enable <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 1236... |
Line 1211... |
// Rule 3 exception 1 - first part (Fault confinement).
|
// Rule 3 exception 1 - first part (Fault confinement).
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rule3_exc1_1 <= 1'b0;
|
rule3_exc1_1 <= 1'b0;
|
else if (reset_mode | error_flag_over | rule3_exc1_2)
|
else if (error_flag_over | rule3_exc1_2)
|
rule3_exc1_1 <=#Tp 1'b0;
|
rule3_exc1_1 <=#Tp 1'b0;
|
else if (transmitter & node_error_passive & ack_err)
|
else if (transmitter & node_error_passive & ack_err)
|
rule3_exc1_1 <=#Tp 1'b1;
|
rule3_exc1_1 <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 1248... |
Line 1223... |
// Rule 3 exception 1 - second part (Fault confinement).
|
// Rule 3 exception 1 - second part (Fault confinement).
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rule3_exc1_2 <= 1'b0;
|
rule3_exc1_2 <= 1'b0;
|
else if (reset_mode | go_error_frame | rule3_exc1_2)
|
else if (go_error_frame | rule3_exc1_2)
|
rule3_exc1_2 <=#Tp 1'b0;
|
rule3_exc1_2 <=#Tp 1'b0;
|
else if (rule3_exc1_1 & (error_cnt1 < 3'd7) & sample_point & (~sampled_bit))
|
else if (rule3_exc1_1 & (error_cnt1 < 3'd7) & sample_point & (~sampled_bit))
|
rule3_exc1_2 <=#Tp 1'b1;
|
rule3_exc1_2 <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 1351... |
Line 1326... |
|
|
|
|
assign header_len[2:0] = extended_mode ? (ide? (3'h5) : (3'h3)) : 3'h2;
|
assign header_len[2:0] = extended_mode ? (ide? (3'h5) : (3'h3)) : 3'h2;
|
assign storing_header = header_cnt < header_len;
|
assign storing_header = header_cnt < header_len;
|
assign limited_data_len_minus1[3:0] = remote_rq? 4'hf : ((data_len < 4'h8)? (data_len -1'b1) : 4'h7); // - 1 because counter counts from 0
|
assign limited_data_len_minus1[3:0] = remote_rq? 4'hf : ((data_len < 4'h8)? (data_len -1'b1) : 4'h7); // - 1 because counter counts from 0
|
assign reset_wr_fifo = (data_cnt == (limited_data_len_minus1 + {1'b0, header_len})) | reset_mode;
|
assign reset_wr_fifo = (data_cnt == (limited_data_len_minus1 + {1'b0, header_len})) || reset_mode;
|
|
|
assign err = form_err | stuff_err | bit_err | ack_err | form_err_latched | stuff_err_latched | bit_err_latched | ack_err_latched | crc_err;
|
assign err = form_err | stuff_err | bit_err | ack_err | form_err_latched | stuff_err_latched | bit_err_latched | ack_err_latched | crc_err;
|
|
|
|
|
|
|
| Line 1451... |
Line 1426... |
// Transmitting error frame.
|
// Transmitting error frame.
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
error_frame <= 1'b0;
|
error_frame <= 1'b0;
|
else if (reset_mode | error_frame_ended | go_overload_frame)
|
// else if (reset_mode || error_frame_ended || go_overload_frame)
|
|
else if (set_reset_mode || error_frame_ended || go_overload_frame)
|
error_frame <=#Tp 1'b0;
|
error_frame <=#Tp 1'b0;
|
else if (go_error_frame)
|
else if (go_error_frame)
|
error_frame <=#Tp 1'b1;
|
error_frame <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
error_cnt1 <= 3'd0;
|
error_cnt1 <= 3'd0;
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
else if (error_frame_ended | go_error_frame | go_overload_frame)
|
error_cnt1 <=#Tp 3'd0;
|
error_cnt1 <=#Tp 3'd0;
|
else if (error_frame & tx_point & (error_cnt1 < 3'd7))
|
else if (error_frame & tx_point & (error_cnt1 < 3'd7))
|
error_cnt1 <=#Tp error_cnt1 + 1'b1;
|
error_cnt1 <=#Tp error_cnt1 + 1'b1;
|
end
|
end
|
|
|
| Line 1477... |
Line 1454... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
error_flag_over_latched <= 1'b0;
|
error_flag_over_latched <= 1'b0;
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
else if (error_frame_ended | go_error_frame | go_overload_frame)
|
error_flag_over_latched <=#Tp 1'b0;
|
error_flag_over_latched <=#Tp 1'b0;
|
else if (error_flag_over)
|
else if (error_flag_over)
|
error_flag_over_latched <=#Tp 1'b1;
|
error_flag_over_latched <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
enable_error_cnt2 <= 1'b0;
|
enable_error_cnt2 <= 1'b0;
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
else if (error_frame_ended | go_error_frame | go_overload_frame)
|
enable_error_cnt2 <=#Tp 1'b0;
|
enable_error_cnt2 <=#Tp 1'b0;
|
else if (error_frame & (error_flag_over & sampled_bit))
|
else if (error_frame & (error_flag_over & sampled_bit))
|
enable_error_cnt2 <=#Tp 1'b1;
|
enable_error_cnt2 <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
error_cnt2 <= 3'd0;
|
error_cnt2 <= 3'd0;
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
else if (error_frame_ended | go_error_frame | go_overload_frame)
|
error_cnt2 <=#Tp 3'd0;
|
error_cnt2 <=#Tp 3'd0;
|
else if (enable_error_cnt2 & tx_point)
|
else if (enable_error_cnt2 & tx_point)
|
error_cnt2 <=#Tp error_cnt2 + 1'b1;
|
error_cnt2 <=#Tp error_cnt2 + 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
delayed_dominant_cnt <= 3'h0;
|
delayed_dominant_cnt <= 3'h0;
|
else if (reset_mode | enable_error_cnt2 | go_error_frame | enable_overload_cnt2 | go_overload_frame)
|
else if (enable_error_cnt2 | go_error_frame | enable_overload_cnt2 | go_overload_frame)
|
delayed_dominant_cnt <=#Tp 3'h0;
|
delayed_dominant_cnt <=#Tp 3'h0;
|
else if (sample_point & (~sampled_bit) & ((error_cnt1 == 3'd7) | (overload_cnt1 == 3'd7)))
|
else if (sample_point & (~sampled_bit) & ((error_cnt1 == 3'd7) | (overload_cnt1 == 3'd7)))
|
delayed_dominant_cnt <=#Tp delayed_dominant_cnt + 1'b1;
|
delayed_dominant_cnt <=#Tp delayed_dominant_cnt + 1'b1;
|
end
|
end
|
|
|
| Line 1522... |
Line 1499... |
// passive_cnt
|
// passive_cnt
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
passive_cnt <= 3'h1;
|
passive_cnt <= 3'h1;
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame | first_compare_bit)
|
else if (error_frame_ended | go_error_frame | go_overload_frame | first_compare_bit)
|
passive_cnt <=#Tp 3'h1;
|
passive_cnt <=#Tp 3'h1;
|
else if (sample_point & (passive_cnt < 3'h6))
|
else if (sample_point & (passive_cnt < 3'h6))
|
begin
|
begin
|
if (error_frame & (~enable_error_cnt2) & (sampled_bit == sampled_bit_q))
|
if (error_frame & (~enable_error_cnt2) & (sampled_bit == sampled_bit_q))
|
passive_cnt <=#Tp passive_cnt + 1'b1;
|
passive_cnt <=#Tp passive_cnt + 1'b1;
|
| Line 1551... |
Line 1528... |
// Transmitting overload frame.
|
// Transmitting overload frame.
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
overload_frame <= 1'b0;
|
overload_frame <= 1'b0;
|
else if (reset_mode | overload_frame_ended | go_error_frame)
|
else if (overload_frame_ended | go_error_frame)
|
overload_frame <=#Tp 1'b0;
|
overload_frame <=#Tp 1'b0;
|
else if (go_overload_frame)
|
else if (go_overload_frame)
|
overload_frame <=#Tp 1'b1;
|
overload_frame <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
overload_cnt1 <= 3'd0;
|
overload_cnt1 <= 3'd0;
|
else if (reset_mode | overload_frame_ended | go_error_frame | go_overload_frame)
|
else if (overload_frame_ended | go_error_frame | go_overload_frame)
|
overload_cnt1 <=#Tp 3'd0;
|
overload_cnt1 <=#Tp 3'd0;
|
else if (overload_frame & tx_point & (overload_cnt1 < 3'd7))
|
else if (overload_frame & tx_point & (overload_cnt1 < 3'd7))
|
overload_cnt1 <=#Tp overload_cnt1 + 1'b1;
|
overload_cnt1 <=#Tp overload_cnt1 + 1'b1;
|
end
|
end
|
|
|
| Line 1576... |
Line 1553... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
enable_overload_cnt2 <= 1'b0;
|
enable_overload_cnt2 <= 1'b0;
|
else if (reset_mode | overload_frame_ended | go_error_frame | go_overload_frame)
|
else if (overload_frame_ended | go_error_frame | go_overload_frame)
|
enable_overload_cnt2 <=#Tp 1'b0;
|
enable_overload_cnt2 <=#Tp 1'b0;
|
else if (overload_frame & (overload_flag_over & sampled_bit))
|
else if (overload_frame & (overload_flag_over & sampled_bit))
|
enable_overload_cnt2 <=#Tp 1'b1;
|
enable_overload_cnt2 <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
overload_cnt2 <= 3'd0;
|
overload_cnt2 <= 3'd0;
|
else if (reset_mode | overload_frame_ended | go_error_frame | go_overload_frame)
|
else if (overload_frame_ended | go_error_frame | go_overload_frame)
|
overload_cnt2 <=#Tp 3'd0;
|
overload_cnt2 <=#Tp 3'd0;
|
else if (enable_overload_cnt2 & tx_point)
|
else if (enable_overload_cnt2 & tx_point)
|
overload_cnt2 <=#Tp overload_cnt2 + 1'b1;
|
overload_cnt2 <=#Tp overload_cnt2 + 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
overload_request_cnt <= 2'b0;
|
overload_request_cnt <= 2'b0;
|
else if (reset_mode | go_error_frame | go_rx_id1)
|
else if (go_error_frame | go_rx_id1)
|
overload_request_cnt <=#Tp 2'b0;
|
overload_request_cnt <=#Tp 2'b0;
|
else if (overload_request & overload_frame)
|
else if (overload_request & overload_frame)
|
overload_request_cnt <=#Tp overload_request_cnt + 1'b1;
|
overload_request_cnt <=#Tp overload_request_cnt + 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
overload_frame_blocked <= 1'b0;
|
overload_frame_blocked <= 1'b0;
|
else if (reset_mode | go_error_frame | go_rx_id1)
|
else if (go_error_frame | go_rx_id1)
|
overload_frame_blocked <=#Tp 1'b0;
|
overload_frame_blocked <=#Tp 1'b0;
|
else if (overload_request & overload_frame & overload_request_cnt == 2'h2) // This is a second sequential overload_request
|
else if (overload_request & overload_frame & overload_request_cnt == 2'h2) // This is a second sequential overload_request
|
overload_frame_blocked <=#Tp 1'b1;
|
overload_frame_blocked <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 1908... |
Line 1885... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
arbitration_lost <= 1'b0;
|
arbitration_lost <= 1'b0;
|
else if (go_rx_idle | error_frame_ended | reset_mode)
|
else if (go_rx_idle | error_frame_ended)
|
arbitration_lost <=#Tp 1'b0;
|
arbitration_lost <=#Tp 1'b0;
|
else if (transmitter & sample_point & tx & arbitration_field & ~sampled_bit)
|
else if (transmitter & sample_point & tx & arbitration_field & ~sampled_bit)
|
arbitration_lost <=#Tp 1'b1;
|
arbitration_lost <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
begin
|
|
arbitration_lost_q <=#Tp 1'b0;
|
|
read_arbitration_lost_capture_reg_q <=#Tp 1'b0;
|
|
end
|
|
else if (reset_mode)
|
|
begin
|
|
arbitration_lost_q <=#Tp 1'b0;
|
arbitration_lost_q <=#Tp 1'b0;
|
read_arbitration_lost_capture_reg_q <=#Tp 1'b0;
|
|
end
|
|
else
|
else
|
begin
|
|
arbitration_lost_q <=#Tp arbitration_lost;
|
arbitration_lost_q <=#Tp arbitration_lost;
|
read_arbitration_lost_capture_reg_q <=#Tp read_arbitration_lost_capture_reg;
|
|
end
|
end
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
|
begin
|
|
if (rst)
|
|
arbitration_field_d <=#Tp 1'b0;
|
|
else if (sample_point)
|
|
arbitration_field_d <=#Tp arbitration_field;
|
end
|
end
|
|
|
|
|
assign set_arbitration_lost_irq = arbitration_lost & (~arbitration_lost_q) & (~arbitration_blocked);
|
assign set_arbitration_lost_irq = arbitration_lost & (~arbitration_lost_q) & (~arbitration_blocked);
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
arbitration_cnt_en <= 1'b0;
|
arbitration_cnt <= 5'h0;
|
else if (reset_mode || arbitration_blocked)
|
else if (sample_point && !bit_de_stuff)
|
arbitration_cnt_en <=#Tp 1'b0;
|
if (arbitration_field_d)
|
else if (rx_id1 & sample_point & (~arbitration_blocked))
|
arbitration_cnt <=#Tp arbitration_cnt + 1'b1;
|
arbitration_cnt_en <=#Tp 1'b1;
|
else
|
|
arbitration_cnt <=#Tp 5'h0;
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
arbitration_blocked <= 1'b0;
|
arbitration_lost_capture <= 5'h0;
|
else if (reset_mode || read_arbitration_lost_capture_reg)
|
|
arbitration_blocked <=#Tp 1'b0;
|
|
else if (set_arbitration_lost_irq)
|
else if (set_arbitration_lost_irq)
|
arbitration_blocked <=#Tp 1'b1;
|
arbitration_lost_capture <=#Tp arbitration_cnt;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
arbitration_lost_capture <= 5'h0;
|
arbitration_blocked <= 1'b0;
|
else if (read_arbitration_lost_capture_reg_q)
|
else if (read_arbitration_lost_capture_reg)
|
arbitration_lost_capture <=#Tp 5'h0;
|
arbitration_blocked <=#Tp 1'b0;
|
else if (sample_point & (~arbitration_blocked) & arbitration_cnt_en & (~bit_de_stuff))
|
else if (set_arbitration_lost_irq)
|
arbitration_lost_capture <=#Tp arbitration_lost_capture + 1'b1;
|
arbitration_blocked <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_err_cnt <= 9'h0;
|
rx_err_cnt <= 9'h0;
|
else if (we_rx_err_cnt & (~node_bus_off))
|
else if (we_rx_err_cnt & (~node_bus_off))
|
| Line 2063... |
Line 2035... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bus_free_cnt <= 4'h0;
|
bus_free_cnt <= 4'h0;
|
else if (reset_mode)
|
|
bus_free_cnt <=#Tp 4'h0;
|
|
else if (sample_point)
|
else if (sample_point)
|
begin
|
begin
|
if (sampled_bit & bus_free_cnt_en & (bus_free_cnt < 4'd10))
|
if (sampled_bit & bus_free_cnt_en & (bus_free_cnt < 4'd10))
|
bus_free_cnt <=#Tp bus_free_cnt + 1'b1;
|
bus_free_cnt <=#Tp bus_free_cnt + 1'b1;
|
else
|
else
|
| Line 2090... |
Line 2060... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bus_free <= 1'b0;
|
bus_free <= 1'b0;
|
else if (reset_mode)
|
else if (sample_point & sampled_bit & (bus_free_cnt==4'd10) && waiting_for_bus_free)
|
bus_free <= 1'b0;
|
|
else if (sample_point & sampled_bit & (bus_free_cnt==4'd10))
|
|
bus_free <=#Tp 1'b1;
|
bus_free <=#Tp 1'b1;
|
else
|
else
|
bus_free <=#Tp 1'b0;
|
bus_free <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
waiting_for_bus_free <= 1'b1;
|
waiting_for_bus_free <= 1'b1;
|
else if (reset_mode)
|
|
waiting_for_bus_free <= 1'b1;
|
|
else if (bus_free & (~node_bus_off))
|
else if (bus_free & (~node_bus_off))
|
waiting_for_bus_free <=#Tp 1'b0;
|
waiting_for_bus_free <=#Tp 1'b0;
|
else if ((~reset_mode) & reset_mode_q | node_bus_off_q & (~reset_mode))
|
else if (node_bus_off_q & (~reset_mode))
|
waiting_for_bus_free <=#Tp 1'b1;
|
waiting_for_bus_free <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
assign bus_off_on = ~node_bus_off;
|
assign bus_off_on = ~node_bus_off;
|
