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[/] [can/] [trunk/] [rtl/] [verilog/] [can_bsp.v] - Diff between revs 93 and 95
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| Rev 93 |
Rev 95 |
| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.34 2003/06/22 09:43:03 mohor
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// synthesis full_case parallel_case fixed.
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//
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// Revision 1.33 2003/06/21 12:16:30 mohor
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// Revision 1.33 2003/06/21 12:16:30 mohor
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// paralel_case and full_case compiler directives added to case statements.
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// paralel_case and full_case compiler directives added to case statements.
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//
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//
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// Revision 1.32 2003/06/17 14:28:32 mohor
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// Revision 1.32 2003/06/17 14:28:32 mohor
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// Form error was detected when stuff bit occured at the end of crc.
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// Form error was detected when stuff bit occured at the end of crc.
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| Line 282... |
Line 285... |
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/* Tx signal */
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/* Tx signal */
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tx,
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tx,
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tx_oen
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tx_oen
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/* Bist */
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`ifdef CAN_BIST
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,
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scanb_rst,
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scanb_clk,
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scanb_si,
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scanb_so,
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scanb_en
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`endif
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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input clk;
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input clk;
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| Line 393... |
Line 405... |
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/* Tx signal */
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/* Tx signal */
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output tx;
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output tx;
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output tx_oen;
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output tx_oen;
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/* Bist */
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`ifdef CAN_BIST
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input scanb_rst;
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input scanb_clk;
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input scanb_si;
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output scanb_so;
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input scanb_en;
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`endif
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reg reset_mode_q;
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reg reset_mode_q;
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reg [5:0] bit_cnt;
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reg [5:0] bit_cnt;
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reg [3:0] data_len;
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reg [3:0] data_len;
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reg [28:0] id;
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reg [28:0] id;
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| Line 1348... |
Line 1369... |
.release_buffer(release_buffer),
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.release_buffer(release_buffer),
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.extended_mode(extended_mode),
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.extended_mode(extended_mode),
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.overrun(overrun),
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.overrun(overrun),
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.info_empty(info_empty),
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.info_empty(info_empty),
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.info_cnt(rx_message_counter)
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.info_cnt(rx_message_counter)
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`ifdef CAN_BIST
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,
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.scanb_rst(scanb_rst),
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.scanb_clk(scanb_clk),
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.scanb_si(scanb_si),
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.scanb_so(scanb_so),
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.scanb_en(scanb_en)
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`endif
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);
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);
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// Transmitting error frame.
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// Transmitting error frame.
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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