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[/] [can/] [trunk/] [rtl/] [verilog/] [can_btl.v] - Diff between revs 100 and 102
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| Rev 100 |
Rev 102 |
| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.21 2003/07/03 09:32:20 mohor
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// Synchronization changed.
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//
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// Revision 1.20 2003/06/20 14:51:11 mohor
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// Revision 1.20 2003/06/20 14:51:11 mohor
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// Previous change removed. When resynchronization occurs we go to seg1
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// Previous change removed. When resynchronization occurs we go to seg1
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// stage. sync stage does not cause another start of seg1 stage.
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// stage. sync stage does not cause another start of seg1 stage.
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//
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//
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// Revision 1.19 2003/06/20 14:28:20 mohor
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// Revision 1.19 2003/06/20 14:28:20 mohor
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| Line 127... |
Line 130... |
(
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(
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clk,
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clk,
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rst,
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rst,
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rx,
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rx,
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/* Mode register */
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reset_mode,
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/* Bus Timing 0 register */
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/* Bus Timing 0 register */
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baud_r_presc,
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baud_r_presc,
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sync_jump_width,
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sync_jump_width,
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/* Bus Timing 1 register */
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/* Bus Timing 1 register */
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| Line 160... |
Line 160... |
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input clk;
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input clk;
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input rst;
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input rst;
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input rx;
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input rx;
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/* Mode register */
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input reset_mode;
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/* Bus Timing 0 register */
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/* Bus Timing 0 register */
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input [5:0] baud_r_presc;
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input [5:0] baud_r_presc;
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input [1:0] sync_jump_width;
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input [1:0] sync_jump_width;
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