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[/] [can/] [trunk/] [rtl/] [verilog/] [can_btl.v] - Diff between revs 104 and 106

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Rev 104	Rev 106
Line 48...	Line 48...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.23 2003/07/10 01:59:04 tadejm`
	`// Synchronization fixed. In some strange cases it didn't work according to`
	`// the VHDL reference model.`
	`//`
`// Revision 1.22 2003/07/07 11:21:37 mohor`	`// Revision 1.22 2003/07/07 11:21:37 mohor`
`// Little fixes (to fix warnings).`	`// Little fixes (to fix warnings).`
`//`	`//`
`// Revision 1.21 2003/07/03 09:32:20 mohor`	`// Revision 1.21 2003/07/03 09:32:20 mohor`
`// Synchronization changed.`	`// Synchronization changed.`
Line 152...	Line 156...
`hard_sync,`	`hard_sync,`

`/* Output from can_bsp module */`	`/* Output from can_bsp module */`
`rx_idle,`	`rx_idle,`
`not_first_bit_of_inter,`	`not_first_bit_of_inter,`
`transmitting,`	`transmitting`
`go_rx_inter`

`);`	`);`

`parameter Tp = 1;`	`parameter Tp = 1;`

Line 177...	Line 180...

`/* Output from can_bsp module */`	`/* Output from can_bsp module */`
`input rx_idle;`	`input rx_idle;`
`input not_first_bit_of_inter;`	`input not_first_bit_of_inter;`
`input transmitting;`	`input transmitting;`
`input go_rx_inter;`

`/* Output signals from this module */`	`/* Output signals from this module */`
`output sample_point;`	`output sample_point;`
`output sampled_bit;`	`output sampled_bit;`
`output sampled_bit_q;`	`output sampled_bit_q;`
Line 440...	Line 442...
`begin`	`begin`
`if (rst)`	`if (rst)`
`hard_sync_blocked <=#Tp 1'b0;`	`hard_sync_blocked <=#Tp 1'b0;`
`else if (hard_sync & clk_en_q)`	`else if (hard_sync & clk_en_q)`
`hard_sync_blocked <=#Tp 1'b1;`	`hard_sync_blocked <=#Tp 1'b1;`
`// else if (go_rx_inter)`
`else if (go_seg2)`	`else if (go_seg2)`
`hard_sync_blocked <=#Tp 1'b0;`	`hard_sync_blocked <=#Tp 1'b0;`
`end`	`end`

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[/] [can/] [trunk/] [rtl/] [verilog/] [can_btl.v] - Diff between revs 104 and 106