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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.28 2004/02/08 14:25:26 mohor
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// Header changed.
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//
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// Revision 1.27 2003/09/30 00:55:13 mohor
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// Revision 1.27 2003/09/30 00:55:13 mohor
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// Error counters fixed to be compatible with Bosch VHDL reference model.
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// Error counters fixed to be compatible with Bosch VHDL reference model.
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// Small synchronization changes.
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// Small synchronization changes.
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//
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//
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// Revision 1.26 2003/09/25 18:55:49 mohor
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// Revision 1.26 2003/09/25 18:55:49 mohor
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Line 223... |
output sampled_bit;
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output sampled_bit;
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output sampled_bit_q;
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output sampled_bit_q;
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output tx_point;
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output tx_point;
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output hard_sync;
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output hard_sync;
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reg [6:0] clk_cnt;
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reg [6:0] clk_cnt;
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reg clk_en;
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reg clk_en;
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reg clk_en_q;
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reg clk_en_q;
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reg sync_blocked;
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reg sync_blocked;
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reg hard_sync_blocked;
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reg hard_sync_blocked;
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Line 249... |
wire [7:0] preset_cnt;
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wire [7:0] preset_cnt;
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wire sync_window;
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wire sync_window;
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wire resync;
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wire resync;
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assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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assign hard_sync = (rx_idle | rx_inter) & (~rx) & sampled_bit & (~hard_sync_blocked); // Hard synchronization
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assign hard_sync = (rx_idle | rx_inter) & (~rx) & sampled_bit & (~hard_sync_blocked); // Hard synchronization
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assign resync = (~rx_idle) & (~rx_inter) & (~rx) & sampled_bit & (~sync_blocked); // Re-synchronization
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assign resync = (~rx_idle) & (~rx_inter) & (~rx) & sampled_bit & (~sync_blocked); // Re-synchronization
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/* Generating general enable signal that defines baud rate. */
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/* Generating general enable signal that defines baud rate. */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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clk_cnt <= 7'h0;
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clk_cnt <= 7'h0;
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Line 302... |
begin
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begin
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if (rst)
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if (rst)
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tx_point <= 1'b0;
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tx_point <= 1'b0;
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else
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else
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tx_point <=#Tp ~tx_point & seg2 & ( clk_en & (quant_cnt[2:0] == time_segment2)
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tx_point <=#Tp ~tx_point & seg2 & ( clk_en & (quant_cnt[2:0] == time_segment2)
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| clk_en_q & (resync | hard_sync)
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| (clk_en | clk_en_q) & (resync | hard_sync)
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); // When transmitter we should transmit as soon as possible.
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); // When transmitter we should transmit as soon as possible.
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end
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end
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/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
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/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
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SJW is reached */
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SJW is reached */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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Line 403... |
begin
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begin
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sampled_bit <= 1'b1;
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sampled_bit <= 1'b1;
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sampled_bit_q <= 1'b1;
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sampled_bit_q <= 1'b1;
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sample_point <= 1'b0;
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sample_point <= 1'b0;
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end
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end
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else if (go_error_frame)
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begin
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sampled_bit_q <=#Tp sampled_bit;
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sample_point <=#Tp 1'b0;
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end
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else if (clk_en_q & (~hard_sync))
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else if (clk_en_q & (~hard_sync))
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begin
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begin
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if (seg1 & (quant_cnt == (time_segment1 + delay)))
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if (seg1 & (quant_cnt == (time_segment1 + delay)))
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begin
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begin
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sample_point <=#Tp 1'b1;
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sample_point <=#Tp 1'b1;
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Line 462... |
/* Blocking hard synchronization when occurs once or when we are transmitting a msg */
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/* Blocking hard synchronization when occurs once or when we are transmitting a msg */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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hard_sync_blocked <=#Tp 1'b0;
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hard_sync_blocked <=#Tp 1'b0;
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else if (hard_sync & clk_en_q | transmitting & transmitter & tx_point & (~tx_next))
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else if (hard_sync & clk_en_q | (transmitting & transmitter | go_tx) & tx_point & (~tx_next))
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hard_sync_blocked <=#Tp 1'b1;
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hard_sync_blocked <=#Tp 1'b1;
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else if (go_rx_inter | (rx_idle | rx_inter) & sample_point & sampled_bit) // When a glitch performed synchronization
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else if (go_rx_inter | (rx_idle | rx_inter) & sample_point & sampled_bit) // When a glitch performed synchronization
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hard_sync_blocked <=#Tp 1'b0;
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hard_sync_blocked <=#Tp 1'b0;
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end
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end
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endmodule
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endmodule
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