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[/] [can/] [trunk/] [rtl/] [verilog/] [can_btl.v] - Diff between revs 141 and 149
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| Rev 141 |
Rev 149 |
| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.29 2004/05/12 15:58:41 igorm
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// Core improved to pass all tests with the Bosch VHDL Reference system.
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//
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// Revision 1.28 2004/02/08 14:25:26 mohor
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// Revision 1.28 2004/02/08 14:25:26 mohor
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// Header changed.
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// Header changed.
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//
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//
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// Revision 1.27 2003/09/30 00:55:13 mohor
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// Revision 1.27 2003/09/30 00:55:13 mohor
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// Error counters fixed to be compatible with Bosch VHDL reference model.
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// Error counters fixed to be compatible with Bosch VHDL reference model.
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| Line 230... |
Line 233... |
reg clk_en_q;
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reg clk_en_q;
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reg sync_blocked;
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reg sync_blocked;
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reg hard_sync_blocked;
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reg hard_sync_blocked;
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reg sampled_bit;
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reg sampled_bit;
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reg sampled_bit_q;
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reg sampled_bit_q;
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reg [3:0] quant_cnt;
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reg [4:0] quant_cnt;
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reg [3:0] delay;
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reg [3:0] delay;
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reg sync;
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reg sync;
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reg seg1;
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reg seg1;
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reg seg2;
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reg seg2;
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reg resync_latched;
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reg resync_latched;
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| Line 360... |
Line 363... |
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/* Quant counter */
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/* Quant counter */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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quant_cnt <= 4'h0;
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quant_cnt <= 5'h0;
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else if (go_sync | go_seg1 | go_seg2)
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else if (go_sync | go_seg1 | go_seg2)
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quant_cnt <=#Tp 4'h0;
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quant_cnt <=#Tp 5'h0;
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else if (clk_en_q)
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else if (clk_en_q)
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quant_cnt <=#Tp quant_cnt + 1'b1;
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quant_cnt <=#Tp quant_cnt + 1'b1;
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end
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end
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| Line 374... |
Line 377... |
always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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delay <= 4'h0;
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delay <= 4'h0;
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else if (resync & seg1 & (~transmitting | transmitting & (tx_next_sp | (tx & (~rx))))) // when transmitting 0 with positive error delay is set to 0
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else if (resync & seg1 & (~transmitting | transmitting & (tx_next_sp | (tx & (~rx))))) // when transmitting 0 with positive error delay is set to 0
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delay <=#Tp (quant_cnt > {2'h0, sync_jump_width})? ({2'h0, sync_jump_width} + 1'b1) : (quant_cnt + 1'b1);
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delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? ({2'h0, sync_jump_width} + 1'b1) : (quant_cnt + 1'b1);
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else if (go_sync | go_seg1)
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else if (go_sync | go_seg1)
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delay <=#Tp 4'h0;
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delay <=#Tp 4'h0;
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end
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end
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