| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.14 2003/06/13 14:55:11 mohor
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// Counters width changed.
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//
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// Revision 1.13 2003/06/11 14:21:35 mohor
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// Revision 1.13 2003/06/11 14:21:35 mohor
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// When switching to tx, sync stage is overjumped.
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// When switching to tx, sync stage is overjumped.
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//
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//
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// Revision 1.12 2003/02/14 20:17:01 mohor
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// Revision 1.12 2003/02/14 20:17:01 mohor
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// Several registers added. Not finished, yet.
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// Several registers added. Not finished, yet.
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| Line 126... |
Line 129... |
hard_sync,
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hard_sync,
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go_seg1,
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go_seg1,
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/* Output from can_bsp module */
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/* Output from can_bsp module */
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rx_idle,
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rx_idle,
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transmitting,
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overjump_sync_seg,
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overjump_sync_seg,
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last_bit_of_inter
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last_bit_of_inter
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| Line 156... |
Line 158... |
input [2:0] time_segment2;
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input [2:0] time_segment2;
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input triple_sampling;
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input triple_sampling;
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/* Output from can_bsp module */
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/* Output from can_bsp module */
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input rx_idle;
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input rx_idle;
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input transmitting;
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input overjump_sync_seg;
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input overjump_sync_seg;
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input last_bit_of_inter;
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input last_bit_of_inter;
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/* Output signals from this module */
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/* Output signals from this module */
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output clk_en;
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output clk_en;
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Line 200... |
wire quant_cnt_rst2;
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wire quant_cnt_rst2;
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assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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assign hard_sync = (rx_idle | last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked) & (~transmitting); // Hard synchronization
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assign hard_sync = (rx_idle | last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked); // Hard synchronization
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assign resync = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked) & (~transmitting); // Re-synchronization
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assign resync = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked); // Re-synchronization
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/* Generating general enable signal that defines baud rate. */
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/* Generating general enable signal that defines baud rate. */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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