| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.16 2003/06/16 13:57:58 mohor
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// tx_point generated one clk earlier. rx_i registered. Data corrected when
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// using extended mode.
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//
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// Revision 1.15 2003/06/13 15:02:24 mohor
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// Revision 1.15 2003/06/13 15:02:24 mohor
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// Synchronization is also needed when transmitting a message.
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// Synchronization is also needed when transmitting a message.
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//
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//
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// Revision 1.14 2003/06/13 14:55:11 mohor
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// Revision 1.14 2003/06/13 14:55:11 mohor
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// Counters width changed.
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// Counters width changed.
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| Line 127... |
Line 131... |
sample_point,
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sample_point,
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sampled_bit,
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sampled_bit,
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sampled_bit_q,
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sampled_bit_q,
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tx_point,
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tx_point,
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hard_sync,
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hard_sync,
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go_seg1,
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/* Output from can_bsp module */
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/* Output from can_bsp module */
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rx_idle,
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rx_idle,
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overjump_sync_seg,
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last_bit_of_inter
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last_bit_of_inter
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| Line 160... |
Line 162... |
input [2:0] time_segment2;
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input [2:0] time_segment2;
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input triple_sampling;
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input triple_sampling;
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/* Output from can_bsp module */
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/* Output from can_bsp module */
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input rx_idle;
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input rx_idle;
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input overjump_sync_seg;
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input last_bit_of_inter;
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input last_bit_of_inter;
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/* Output signals from this module */
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/* Output signals from this module */
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output sample_point;
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output sample_point;
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output sampled_bit;
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output sampled_bit;
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output sampled_bit_q;
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output sampled_bit_q;
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output tx_point;
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output tx_point;
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output hard_sync;
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output hard_sync;
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output go_seg1;
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reg [8:0] clk_cnt;
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reg [8:0] clk_cnt;
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reg clk_en;
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reg clk_en;
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Line 196... |
wire go_seg1;
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wire go_seg1;
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wire go_seg2;
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wire go_seg2;
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wire [8:0] preset_cnt;
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wire [8:0] preset_cnt;
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wire sync_window;
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wire sync_window;
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wire resync;
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wire resync;
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wire quant_cnt_rst1;
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wire quant_cnt_rst;
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wire quant_cnt_rst2;
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assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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assign hard_sync = (rx_idle | last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked); // Hard synchronization
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assign hard_sync = (rx_idle | last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked); // Hard synchronization
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Line 307... |
seg2 <=#Tp 1'b0;
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seg2 <=#Tp 1'b0;
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end
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end
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/* Quant counter */
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/* Quant counter */
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assign quant_cnt_rst = go_sync | go_seg1 | go_seg2;
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//assign quant_cnt_rst1 = go_sync | go_seg1 & (~overjump_sync_seg) | go_seg2;
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//assign quant_cnt_rst2 = go_seg1 & overjump_sync_seg;
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assign quant_cnt_rst1 = go_sync | go_seg1 | go_seg2;
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assign quant_cnt_rst2 = 1'b0;
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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quant_cnt <= 0;
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quant_cnt <= 0;
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else if (quant_cnt_rst1)
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else if (quant_cnt_rst)
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quant_cnt <=#Tp 0;
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quant_cnt <=#Tp 0;
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else if (quant_cnt_rst2)
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quant_cnt <=#Tp 1;
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else if (clk_en_q)
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else if (clk_en_q)
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quant_cnt <=#Tp quant_cnt + 1'b1;
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quant_cnt <=#Tp quant_cnt + 1'b1;
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end
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end
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