URL https://opencores.org/ocsvn/can/can/trunk

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[/] [can/] [trunk/] [rtl/] [verilog/] [can_btl.v] - Diff between revs 82 and 84

Rev 82	Rev 84
Line 48...	Line 48...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.17 2003/06/17 14:32:17 mohor`
	`// Removed few signals.`
	`//`
`// Revision 1.16 2003/06/16 13:57:58 mohor`	`// Revision 1.16 2003/06/16 13:57:58 mohor`
`// tx_point generated one clk earlier. rx_i registered. Data corrected when`	`// tx_point generated one clk earlier. rx_i registered. Data corrected when`
`// using extended mode.`	`// using extended mode.`
`//`	`//`
`// Revision 1.15 2003/06/13 15:02:24 mohor`	`// Revision 1.15 2003/06/13 15:02:24 mohor`
Line 173...	Line 176...
`output tx_point;`	`output tx_point;`
`output hard_sync;`	`output hard_sync;`



`reg [8:0] clk_cnt;`	`reg [6:0] clk_cnt;`
`reg clk_en;`	`reg clk_en;`
`reg clk_en_q;`	`reg clk_en_q;`
`reg sync_blocked;`	`reg sync_blocked;`
`reg resync_blocked;`	`reg resync_blocked;`
`reg sampled_bit;`	`reg sampled_bit;`