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[/] [can/] [trunk/] [rtl/] [verilog/] [can_defines.v] - Diff between revs 95 and 115
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Rev 115 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2003/06/27 20:56:15 simons
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// Virtual silicon ram instances added.
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//
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// Revision 1.8 2003/06/09 11:32:36 mohor
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// Revision 1.8 2003/06/09 11:32:36 mohor
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// Ports added for the CAN_BIST.
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// Ports added for the CAN_BIST.
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//
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//
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// Revision 1.7 2003/03/20 16:51:55 mohor
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// Revision 1.7 2003/03/20 16:51:55 mohor
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// *** empty log message ***
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// *** empty log message ***
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`define ACTEL_APA_RAM
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`define ACTEL_APA_RAM
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// Uncomment following line if you want to use CAN in Xilinx devices (embedded memory used)
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// Uncomment following line if you want to use CAN in Xilinx devices (embedded memory used)
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// `define XILINX_RAM
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// `define XILINX_RAM
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// Uncomment following line if you want to use CAN in Xilinx devices (embedded memory used)
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// Uncomment the line for the ram used in ASIC implementation
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// `define VIRTUALSILICON_RAM
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// `define VIRTUALSILICON_RAM
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// `define ARTISAN_RAM
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// Uncomment the following line when RAM BIST is needed (ASIC implementation)
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// Uncomment the following line when RAM BIST is needed (ASIC implementation)
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//`define CAN_BIST // Bist (for ASIC implementation)
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//`define CAN_BIST // Bist (for ASIC implementation)
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No newline at end of file
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