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[/] [can/] [trunk/] [rtl/] [verilog/] [can_defines.v] - Diff between revs 124 and 130

Rev 124	Rev 130
Line 48...	Line 48...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.11 2003/09/05 12:46:42 mohor`
	`// ALTERA_RAM supported.`
	`//`
`// Revision 1.10 2003/08/14 16:04:52 simons`	`// Revision 1.10 2003/08/14 16:04:52 simons`
`// Artisan ram instances added.`	`// Artisan ram instances added.`
`//`	`//`
`// Revision 1.9 2003/06/27 20:56:15 simons`	`// Revision 1.9 2003/06/27 20:56:15 simons`
`// Virtual silicon ram instances added.`	`// Virtual silicon ram instances added.`
Line 104...	Line 107...
// `define ARTISAN_RAM	// `define ARTISAN_RAM

`// Uncomment the following line when RAM BIST is needed (ASIC implementation)`	`// Uncomment the following line when RAM BIST is needed (ASIC implementation)`
//`define CAN_BIST // Bist (for ASIC implementation)	//`define CAN_BIST // Bist (for ASIC implementation)

`No newline at end of file`	`No newline at end of file`
	`/* width of MBIST control bus */`
	`define CAN_MBIST_CTRL_WIDTH 3

`No newline at end of file`	`No newline at end of file`