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[/] [can/] [trunk/] [rtl/] [verilog/] [can_defines.v] - Diff between revs 64 and 71

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Rev 64 Rev 71
Line 48... Line 48...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.7  2003/03/20 16:51:55  mohor
 
// *** empty log message ***
 
//
// Revision 1.6  2003/03/12 04:19:13  mohor
// Revision 1.6  2003/03/12 04:19:13  mohor
// 8051 interface added (besides WISHBONE interface). Selection is made in
// 8051 interface added (besides WISHBONE interface). Selection is made in
// can_defines.v file.
// can_defines.v file.
//
//
// Revision 1.5  2003/03/05 15:03:20  mohor
// Revision 1.5  2003/03/05 15:03:20  mohor
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 `define   ACTEL_APA_RAM
 `define   ACTEL_APA_RAM
 
 
// Uncomment following line if you want to use CAN in Xilinx devices (embedded memory used)
// Uncomment following line if you want to use CAN in Xilinx devices (embedded memory used)
// `define   XILINX_RAM
// `define   XILINX_RAM
 
 
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// Uncomment the following line when RAM BIST is needed (ASIC implementation)
 
//`define CAN_BIST                    // Bist (for ASIC implementation)
 
 
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