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[/] [can/] [trunk/] [rtl/] [verilog/] [can_fifo.v] - Diff between revs 109 and 115

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Rev 109 Rev 115
Line 48... Line 48... 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
// CVS Revision History
 
//
 
//
 
// $Log: not supported by cvs2svn $
 
// $Log: not supported by cvs2svn $
 
 
 
// Revision 1.20  2003/07/16 14:00:45  mohor
 
 
 
// Fixed according to the linter.
 
 
 
//
 
// Revision 1.19  2003/07/03 09:30:44  mohor
 
// Revision 1.19  2003/07/03 09:30:44  mohor
 
// PCI_BIST replaced with CAN_BIST.
 
// PCI_BIST replaced with CAN_BIST.
 
//
 
//
 
// Revision 1.18  2003/06/27 22:14:23  simons
 
// Revision 1.18  2003/06/27 22:14:23  simons
 
// Overrun fifo implemented with FFs, because it is not possible to create such a memory.
 
// Overrun fifo implemented with FFs, because it is not possible to create such a memory.
Line 178... Line 181... 
 
 
 
 
`ifdef ACTEL_APA_RAM
 
`ifdef ACTEL_APA_RAM
 
`else
 
`else
 
`ifdef XILINX_RAM
 
`ifdef XILINX_RAM
 
`else
 
`else
 
 
 
`ifdef ARTISAN_RAM
 
 
 
  reg           overrun_info[0:63];
 
 
 
`else
 
`ifdef VIRTUALSILICON_RAM
 
`ifdef VIRTUALSILICON_RAM
 
  reg           overrun_info[0:63];
 
  reg           overrun_info[0:63];
 
`else
 
`else
 
  reg     [7:0] fifo [0:63];
 
  reg     [7:0] fifo [0:63];
 
  reg     [3:0] length_fifo[0:63];
 
  reg     [3:0] length_fifo[0:63];
 
  reg           overrun_info[0:63];
 
  reg           overrun_info[0:63];
 
`endif
 
`endif
 
`endif
 
`endif
 
`endif
 
`endif
 
 
 
`endif
 
 
 
 
 
reg     [5:0] rd_pointer;
 
reg     [5:0] rd_pointer;
 
reg     [5:0] wr_pointer;
 
reg     [5:0] wr_pointer;
 
reg     [5:0] read_address;
 
reg     [5:0] read_address;
 
reg     [5:0] wr_info_pointer;
 
reg     [5:0] wr_info_pointer;
Line 556... Line 563... 
 
 
 
 
    // reading overrun
 
    // reading overrun
 
    assign overrun = overrun_info[rd_info_pointer];
 
    assign overrun = overrun_info[rd_info_pointer];
 
 
 
 
 
`else
 
`else
 
 
 
`ifdef ARTISAN_RAM
 
 
 
 
 
 
 
`ifdef CAN_BIST
 
 
 
    art_hstp_64x8_bist fifo
 
 
 
    (
 
 
 
        .CLKR       (clk),
 
 
 
        .CLKW       (clk),
 
 
 
        .AR         (read_address),
 
 
 
        .AW         (wr_pointer),
 
 
 
        .D          (data_in),
 
 
 
        .Q          (data_out),
 
 
 
        .REN        (~fifo_selected),
 
 
 
        .WEN        (~(wr & (~fifo_full))),
 
 
 
        .scanb_rst  (scanb_rst),
 
 
 
        .scanb_clk  (scanb_clk),
 
 
 
        .scanb_si   (scanb_si),
 
 
 
        .scanb_so   (scanb_s_0),
 
 
 
        .scanb_en   (scanb_en)
 
 
 
    );
 
 
 
    art_hstp_64x4_bist info_fifo
 
 
 
    (
 
 
 
        .CLKR       (clk),
 
 
 
        .CLKW       (clk),
 
 
 
        .AR         (rd_info_pointer),
 
 
 
        .AW         (wr_info_pointer),
 
 
 
        .D          (len_cnt & {4{~initialize_memories}}),
 
 
 
        .Q          (length_info),
 
 
 
        .REN        (1'b0),
 
 
 
        .WEN        (~(write_length_info & (~info_full) | initialize_memories)),
 
 
 
        .scanb_rst  (scanb_rst),
 
 
 
        .scanb_clk  (scanb_clk),
 
 
 
        .scanb_si   (scanb_s_0),
 
 
 
        .scanb_so   (scanb_so),
 
 
 
        .scanb_en   (scanb_en)
 
 
 
    );
 
 
 
`else
 
 
 
    art_hsdp_64x8 fifo
 
 
 
    (
 
 
 
        .CENA       (1'b0),
 
 
 
        .CENB       (1'b0),
 
 
 
        .CLKA       (clk),
 
 
 
        .CLKB       (clk),
 
 
 
        .AA         (read_address),
 
 
 
        .AB         (wr_pointer),
 
 
 
        .DA         (8'h00),
 
 
 
        .DB         (data_in),
 
 
 
        .QA         (data_out),
 
 
 
        .QB         (),
 
 
 
        .RENA       (~fifo_selected),
 
 
 
        .RENB       (1'b1),
 
 
 
        .WENA       (1'b1),
 
 
 
        .WENB       (~(wr & (~fifo_full))),
 
 
 
    );
 
 
 
    art_hsdp_64x4 info_fifo
 
 
 
    (
 
 
 
        .CENA       (1'b0),
 
 
 
        .CENB       (1'b0),
 
 
 
        .CLKA       (clk),
 
 
 
        .CLKB       (clk),
 
 
 
        .AA         (rd_info_pointer),
 
 
 
        .AB         (wr_info_pointer),
 
 
 
        .DA         (4'h0),
 
 
 
        .DB         (len_cnt & {4{~initialize_memories}}),
 
 
 
        .QA         (length_info),
 
 
 
        .QB         (),
 
 
 
        .RENA       (1'b0),
 
 
 
        .RENB       (1'b1),
 
 
 
        .WENB       (),
 
 
 
        .WENB       (~(write_length_info & (~info_full) | initialize_memories))
 
 
 
    );
 
 
 
`endif
 
 
 
 
 
 
 
    // overrun_info
 
 
 
    always @ (posedge clk)
 
 
 
    begin
 
 
 
      if (write_length_info & (~info_full) | initialize_memories)
 
 
 
        overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
 
 
 
    end
 
 
 
 
 
 
 
 
 
 
 
    // reading overrun
 
 
 
    assign overrun = overrun_info[rd_info_pointer];
 
 
 
 
 
 
 
`else
 
  // writing data to fifo
 
  // writing data to fifo
 
  always @ (posedge clk)
 
  always @ (posedge clk)
 
  begin
 
  begin
 
    if (wr & (~fifo_full))
 
    if (wr & (~fifo_full))
 
      fifo[wr_pointer] <=#Tp data_in;
 
      fifo[wr_pointer] <=#Tp data_in;
Line 593... Line 684... 
 
 
 
 
 
 
 
 
`endif
 
`endif
 
`endif
 
`endif
 
`endif
 
`endif
 
 
 
`endif
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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