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[/] [can/] [trunk/] [rtl/] [verilog/] [can_fifo.v] - Diff between revs 118 and 124

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Rev 118	Rev 124
Line 48...	Line 48...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.22 2003/08/20 09:59:16 mohor`
	`// Artisan RAM fixed (when not using BIST).`
	`//`
`// Revision 1.21 2003/08/14 16:04:52 simons`	`// Revision 1.21 2003/08/14 16:04:52 simons`
`// Artisan ram instances added.`	`// Artisan ram instances added.`
`//`	`//`
`// Revision 1.20 2003/07/16 14:00:45 mohor`	`// Revision 1.20 2003/07/16 14:00:45 mohor`
`// Fixed according to the linter.`	`// Fixed according to the linter.`
Line 180...	Line 183...
`output scanb_so;`	`output scanb_so;`
`input scanb_en;`	`input scanb_en;`
`wire scanb_s_0;`	`wire scanb_s_0;`
`endif	`endif

	`ifdef ALTERA_RAM
	`else
`ifdef ACTEL_APA_RAM	`ifdef ACTEL_APA_RAM
`else	`else
`ifdef XILINX_RAM	`ifdef XILINX_RAM
`else	`else
`ifdef ARTISAN_RAM	`ifdef ARTISAN_RAM
Line 197...	Line 202...
`reg overrun_info[0:63];`	`reg overrun_info[0:63];`
`endif	`endif
`endif	`endif
`endif	`endif
`endif	`endif
	`endif

`reg [5:0] rd_pointer;`	`reg [5:0] rd_pointer;`
`reg [5:0] wr_pointer;`	`reg [5:0] wr_pointer;`
`reg [5:0] read_address;`	`reg [5:0] read_address;`
`reg [5:0] wr_info_pointer;`	`reg [5:0] wr_info_pointer;`
Line 361...	Line 367...
`else if (&wr_info_pointer)`	`else if (&wr_info_pointer)`
`initialize_memories <=#Tp 1'b0;`	`initialize_memories <=#Tp 1'b0;`
`end`	`end`


	`ifdef ALTERA_RAM
	`// altera_ram_64x8_sync fifo`
	`lpm_ram_dp fifo`
	`(`
	`.q (data_out),`
	`.rdclock (clk),`
	`.wrclock (clk),`
	`.data (data_in),`
	`.wren (~(wr & (~fifo_full))),`
	`.rden (~fifo_selected),`
	`.wraddress (wr_pointer),`
	`.rdaddress (read_address)`
	`);`
	`defparam fifo.lpm_width = 8;`
	`defparam fifo.lpm_widthad = 6;`


	`// altera_ram_64x4_sync info_fifo`
	`lpm_ram_dp info_fifo`
	`(`
	`.q (length_info),`
	`.rdclock (clk),`
	`.wrclock (clk),`
	`.data (len_cnt & {4{~initialize_memories}}),`
	`.wren (~(write_length_info & (~info_full) \| initialize_memories)),`
	`.rden (1'b0), // always enabled`
	`.wraddress (wr_info_pointer),`
	`.rdaddress (rd_info_pointer)`
	`);`
	`defparam info_fifo.lpm_width = 4;`
	`defparam info_fifo.lpm_widthad = 6;`


	`// altera_ram_64x1_sync overrun_fifo`
	`lpm_ram_dp overrun_fifo`
	`(`
	`.q (overrun),`
	`.rdclock (clk),`
	`.wrclock (clk),`
	`.data ((latch_overrun \| (wr & fifo_full)) & (~initialize_memories)),`
	`.wren (~(write_length_info & (~info_full) \| initialize_memories)),`
	`.rden (1'b0), // always enabled`
	`.wraddress (wr_info_pointer),`
	`.rdaddress (rd_info_pointer)`
	`);`
	`defparam overrun_fifo.lpm_width = 1;`
	`defparam overrun_fifo.lpm_widthad = 6;`

	`else
`ifdef ACTEL_APA_RAM	`ifdef ACTEL_APA_RAM
`actel_ram_64x8_sync fifo`	`actel_ram_64x8_sync fifo`
`(`	`(`
`.DO (data_out),`	`.DO (data_out),`
`.RCLOCK (clk),`	`.RCLOCK (clk),`
Line 688...	Line 743...

`endif	`endif
`endif	`endif
`endif	`endif
`endif	`endif
	`endif

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[/] [can/] [trunk/] [rtl/] [verilog/] [can_fifo.v] - Diff between revs 118 and 124