| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.26 2004/02/08 14:30:57 mohor
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// Header changed.
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//
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// Revision 1.25 2003/10/23 16:52:17 mohor
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// Revision 1.25 2003/10/23 16:52:17 mohor
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// Active high/low problem when Altera devices are used. Bug fixed by
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// Active high/low problem when Altera devices are used. Bug fixed by
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// Rojhalat Ibrahim.
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// Rojhalat Ibrahim.
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//
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//
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// Revision 1.24 2003/10/17 05:55:20 markom
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// Revision 1.24 2003/10/17 05:55:20 markom
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| Line 262... |
Line 265... |
if (rst)
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if (rst)
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wr_info_pointer <= 6'h0;
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wr_info_pointer <= 6'h0;
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else if (write_length_info & (~info_full) | initialize_memories)
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else if (write_length_info & (~info_full) | initialize_memories)
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wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
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wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
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else if (reset_mode)
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else if (reset_mode)
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wr_info_pointer <=#Tp 6'h0;
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wr_info_pointer <=#Tp rd_info_pointer;
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end
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end
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// rd_info_pointer
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// rd_info_pointer
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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rd_info_pointer <= 6'h0;
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rd_info_pointer <= 6'h0;
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else if (reset_mode)
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rd_info_pointer <=#Tp 6'h0;
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else if (release_buffer & (~fifo_empty))
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else if (release_buffer & (~fifo_empty))
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rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
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rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
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end
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end
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| Line 286... |
Line 287... |
begin
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begin
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if (rst)
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if (rst)
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rd_pointer <= 5'h0;
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rd_pointer <= 5'h0;
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else if (release_buffer & (~fifo_empty))
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else if (release_buffer & (~fifo_empty))
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rd_pointer <=#Tp rd_pointer + {2'h0, length_info};
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rd_pointer <=#Tp rd_pointer + {2'h0, length_info};
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else if (reset_mode)
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rd_pointer <=#Tp 5'h0;
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end
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end
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// wr_pointer
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// wr_pointer
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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wr_pointer <= 5'h0;
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wr_pointer <= 5'h0;
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else if (reset_mode)
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wr_pointer <=#Tp rd_pointer;
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else if (wr & (~fifo_full))
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else if (wr & (~fifo_full))
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wr_pointer <=#Tp wr_pointer + 1'b1;
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wr_pointer <=#Tp wr_pointer + 1'b1;
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else if (reset_mode)
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wr_pointer <=#Tp 5'h0;
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end
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end
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// latch_overrun
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// latch_overrun
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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| Line 320... |
Line 319... |
// Counting data in fifo
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// Counting data in fifo
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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fifo_cnt <= 7'h0;
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fifo_cnt <= 7'h0;
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else if (reset_mode)
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fifo_cnt <=#Tp 7'h0;
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else if (wr & (~release_buffer) & (~fifo_full))
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else if (wr & (~release_buffer) & (~fifo_full))
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fifo_cnt <=#Tp fifo_cnt + 1'b1;
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fifo_cnt <=#Tp fifo_cnt + 1'b1;
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else if ((~wr) & release_buffer & (~fifo_empty))
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else if ((~wr) & release_buffer & (~fifo_empty))
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fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};
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fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};
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else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
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else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
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fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;
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fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;
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else if (reset_mode)
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fifo_cnt <=#Tp 7'h0;
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end
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end
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assign fifo_full = fifo_cnt == 7'd64;
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assign fifo_full = fifo_cnt == 7'd64;
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assign fifo_empty = fifo_cnt == 7'd0;
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assign fifo_empty = fifo_cnt == 7'd0;
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