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[/] [can/] [trunk/] [rtl/] [verilog/] [can_fifo.v] - Diff between revs 35 and 39
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| Rev 35 |
Rev 39 |
| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.11 2003/02/14 20:17:01 mohor
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// Several registers added. Not finished, yet.
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//
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// Revision 1.10 2003/02/11 00:56:06 mohor
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// Revision 1.10 2003/02/11 00:56:06 mohor
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// Wishbone interface added.
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// Wishbone interface added.
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//
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//
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// Revision 1.9 2003/02/09 02:24:33 mohor
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// Revision 1.9 2003/02/09 02:24:33 mohor
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// Bosch license warning added. Error counters finished. Overload frames
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// Bosch license warning added. Error counters finished. Overload frames
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| Line 106... |
Line 109... |
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reset_mode,
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reset_mode,
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release_buffer,
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release_buffer,
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extended_mode,
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extended_mode,
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overrun,
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overrun,
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info_empty
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info_empty,
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info_cnt
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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| Line 124... |
Line 128... |
input extended_mode;
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input extended_mode;
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output [7:0] data_out;
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output [7:0] data_out;
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output overrun;
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output overrun;
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output info_empty;
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output info_empty;
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output [6:0] info_cnt;
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reg [7:0] fifo [0:63];
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reg [7:0] fifo [0:63];
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reg [5:0] rd_pointer;
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reg [5:0] rd_pointer;
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reg [5:0] wr_pointer;
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reg [5:0] wr_pointer;
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