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//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

//

//

// CVS Revision History

// CVS Revision History

//

//

// $Log: not supported by cvs2svn $

// $Log: not supported by cvs2svn $

// Revision 1.13  2003/03/01 22:53:33  mohor

// Revision 1.13  2003/03/01 22:53:33  mohor

// Actel APA ram supported.

// Actel APA ram supported.

//

//

// Revision 1.12  2003/02/19 14:44:03  mohor

// Revision 1.12  2003/02/19 14:44:03  mohor

// CAN core finished. Host interface added. Registers finished.

// CAN core finished. Host interface added. Registers finished.

reg           wr_q;

reg           wr_q;

reg     [3:0] len_cnt;

reg     [3:0] len_cnt;

reg     [6:0] fifo_cnt;

reg     [6:0] fifo_cnt;

reg     [6:0] info_cnt;

reg     [6:0] info_cnt;

reg           latch_overrun;

reg           latch_overrun;

wire    [3:0] length_info;

wire    [3:0] length_info;

wire          write_length_info;

wire          write_length_info;

wire          fifo_empty;

wire          fifo_empty;

wire          fifo_full;

wire          fifo_full;

// wr_info_pointer

// wr_info_pointer

always @ (posedge clk or posedge rst)

always @ (posedge clk or posedge rst)

begin

begin

  if (rst)

  if (rst)

    wr_info_pointer <= 0;

    wr_info_pointer <= 0;

  else if (reset_mode)

  else if (reset_mode)

    wr_info_pointer <=#Tp 0;

    wr_info_pointer <=#Tp 0;

end

end

// rd_info_pointer

// rd_info_pointer

      read_address <= rd_pointer + (addr - 8'd20);

      read_address <= rd_pointer + (addr - 8'd20);

    end

    end

end

end

`ifdef ACTEL_APA_RAM

`ifdef ACTEL_APA_RAM

  actel_ram_64x8_sync fifo

  actel_ram_64x8_sync fifo

  (

  (

    .DO      (data_out),

    .DO      (data_out),

  actel_ram_64x4_sync info_fifo

  actel_ram_64x4_sync info_fifo

  (

  (

    .DO      (length_info),

    .DO      (length_info),

    .RCLOCK  (clk),

    .RCLOCK  (clk),

    .WCLOCK  (clk),

    .WCLOCK  (clk),

    .PO      (),                       // parity not used

    .PO      (),                       // parity not used

    .RDB     (1'b0),                   // always enabled

    .RDB     (1'b0),                   // always enabled

    .WADDR   (wr_info_pointer),

    .WADDR   (wr_info_pointer),

    .RADDR   (rd_info_pointer)

    .RADDR   (rd_info_pointer)

  );

  );

  actel_ram_64x1_sync overrun_fifo

  actel_ram_64x1_sync overrun_fifo

  (

  (

    .DO      (overrun),

    .DO      (overrun),

    .RCLOCK  (clk),

    .RCLOCK  (clk),

    .WCLOCK  (clk),

    .WCLOCK  (clk),

    .PO      (),                       // parity not used

    .PO      (),                       // parity not used

    .RDB     (1'b0),                   // always enabled

    .RDB     (1'b0),                   // always enabled

    .WADDR   (wr_info_pointer),

    .WADDR   (wr_info_pointer),

    .RADDR   (rd_info_pointer)

    .RADDR   (rd_info_pointer)

  );

  );

`else

`else

  (

  (

    .DOA(),

    .DOA(),

    .DOB(length_info),

    .DOB(length_info),

    .ADDRA({4'h0, wr_info_pointer}),

    .ADDRA({4'h0, wr_info_pointer}),

    .CLKA(clk),

    .CLKA(clk),

    .ENA(1'b1),

    .ENA(1'b1),

    .RSTA(1'b0),

    .RSTA(1'b0),

    .ADDRB({4'h0, rd_info_pointer}),

    .ADDRB({4'h0, rd_info_pointer}),

    .CLKB(clk),

    .CLKB(clk),

    .DIB(4'h0),

    .DIB(4'h0),

    .ENB(1'b1),

    .ENB(1'b1),

    .RSTB(1'b0),

    .RSTB(1'b0),

  (

  (

    .DOA(),

    .DOA(),

    .DOB(overrun),

    .DOB(overrun),

    .ADDRA({6'h0, wr_info_pointer}),

    .ADDRA({6'h0, wr_info_pointer}),

    .CLKA(clk),

    .CLKA(clk),

    .ENA(1'b1),

    .ENA(1'b1),

    .RSTA(1'b0),

    .RSTA(1'b0),

    .ADDRB({6'h0, rd_info_pointer}),

    .ADDRB({6'h0, rd_info_pointer}),

    .CLKB(clk),

    .CLKB(clk),

    .DIB(1'h0),

    .DIB(1'h0),

    .ENB(1'b1),

    .ENB(1'b1),

    .RSTB(1'b0),

    .RSTB(1'b0),

    .WEB(1'b0)

    .WEB(1'b0)

  );

  );

`else

`else

  // writing data to fifo

  // writing data to fifo

  always @ (posedge clk)

  always @ (posedge clk)

  begin

  begin

    if (wr & (~fifo_full))

    if (wr & (~fifo_full))

  // writing length_fifo

  // writing length_fifo

  always @ (posedge clk)

  always @ (posedge clk)

  begin

  begin

  end

  end

  // reading length_fifo

  // reading length_fifo

  assign length_info = length_fifo[rd_info_pointer];

  assign length_info = length_fifo[rd_info_pointer];

  // overrun_info

  // overrun_info

  always @ (posedge clk)

  always @ (posedge clk)

  begin

  begin

  end

  end

  // reading overrun

  // reading overrun

  assign overrun = overrun_info[rd_info_pointer];

  assign overrun = overrun_info[rd_info_pointer];