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[/] [can/] [trunk/] [rtl/] [verilog/] [can_fifo.v] - Diff between revs 73 and 85
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| Rev 73 |
Rev 85 |
| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.15 2003/06/11 09:37:05 mohor
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// overrun and length_info fifos are initialized at the end of reset.
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//
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// Revision 1.14 2003/03/05 15:02:30 mohor
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// Revision 1.14 2003/03/05 15:02:30 mohor
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// Xilinx RAM added.
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// Xilinx RAM added.
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//
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//
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// Revision 1.13 2003/03/01 22:53:33 mohor
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// Revision 1.13 2003/03/01 22:53:33 mohor
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// Actel APA ram supported.
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// Actel APA ram supported.
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Line 475... |
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// writing length_fifo
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// writing length_fifo
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (write_length_info & (~info_full) | initialize_memories))
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if (write_length_info & (~info_full) | initialize_memories)
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length_fifo[wr_info_pointer] <=#Tp len_cnt & {4{~initialize_memories}};
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length_fifo[wr_info_pointer] <=#Tp len_cnt & {4{~initialize_memories}};
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end
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end
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// reading length_fifo
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// reading length_fifo
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