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[/] [can/] [trunk/] [rtl/] [verilog/] [can_fifo.v] - Diff between revs 85 and 95

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Rev 85 Rev 95
Line 48... Line 48... 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
// CVS Revision History
 
//
 
//
 
// $Log: not supported by cvs2svn $
 
// $Log: not supported by cvs2svn $
 
 
 
// Revision 1.16  2003/06/18 23:03:44  mohor
 
 
 
// Typo fixed.
 
 
 
//
 
// Revision 1.15  2003/06/11 09:37:05  mohor
 
// Revision 1.15  2003/06/11 09:37:05  mohor
 
// overrun and length_info fifos are initialized at the end of reset.
 
// overrun and length_info fifos are initialized at the end of reset.
 
//
 
//
 
// Revision 1.14  2003/03/05 15:02:30  mohor
 
// Revision 1.14  2003/03/05 15:02:30  mohor
 
// Xilinx RAM added.
 
// Xilinx RAM added.
Line 126... Line 129... 
  extended_mode,
 
  extended_mode,
 
  overrun,
 
  overrun,
 
  info_empty,
 
  info_empty,
 
  info_cnt
 
  info_cnt
 
 
 
 
 
 
 
`ifdef CAN_BIST
 
 
 
  ,
 
 
 
  scanb_rst,
 
 
 
  scanb_clk,
 
 
 
  scanb_si,
 
 
 
  scanb_so,
 
 
 
  scanb_en
 
 
 
`endif
 
);
 
);
 
 
 
 
 
parameter Tp = 1;
 
parameter Tp = 1;
 
 
 
 
 
input         clk;
 
input         clk;
Line 145... Line 156... 
output  [7:0] data_out;
 
output  [7:0] data_out;
 
output        overrun;
 
output        overrun;
 
output        info_empty;
 
output        info_empty;
 
output  [6:0] info_cnt;
 
output  [6:0] info_cnt;
 
 
 
 
 
 
 
`ifdef CAN_BIST
 
 
 
input         scanb_rst;
 
 
 
input         scanb_clk;
 
 
 
input         scanb_si;
 
 
 
output        scanb_so;
 
 
 
input         scanb_en;
 
 
 
wire          scanb_s_0;
 
 
 
wire          scanb_s_1;
 
 
 
`endif
 
 
 
 
 
`ifdef ACTEL_APA_RAM
 
`ifdef ACTEL_APA_RAM
 
`else
 
`else
 
`ifdef XILINX_RAM
 
`ifdef XILINX_RAM
 
`else
 
`else
 
 
 
`ifdef VIRTUALSILICON_RAM
 
 
 
`else
 
  reg     [7:0] fifo [0:63];
 
  reg     [7:0] fifo [0:63];
 
  reg     [3:0] length_fifo[0:63];
 
  reg     [3:0] length_fifo[0:63];
 
  reg           overrun_info[0:63];
 
  reg           overrun_info[0:63];
 
`endif
 
`endif
 
`endif
 
`endif
 
 
 
`endif
 
 
 
 
 
reg     [5:0] rd_pointer;
 
reg     [5:0] rd_pointer;
 
reg     [5:0] wr_pointer;
 
reg     [5:0] wr_pointer;
 
reg     [5:0] read_address;
 
reg     [5:0] read_address;
 
reg     [5:0] wr_info_pointer;
 
reg     [5:0] wr_info_pointer;
Line 461... Line 485... 
    .WEB(1'b0)
 
    .WEB(1'b0)
 
  );
 
  );
 
 
 
 
 
 
 
 
 
`else
 
`else
 
 
 
`ifdef VIRTUALSILICON_RAM
 
 
 
 
 
 
 
`ifdef PCI_BIST
 
 
 
    vs_hdtp_64x8_bist fifo
 
 
 
`else
 
 
 
    vs_hdtp_64x8 fifo
 
 
 
`endif
 
 
 
    (
 
 
 
        .RCK        (clk),
 
 
 
        .WCK        (clk),
 
 
 
        .RADR       (read_address),
 
 
 
        .WADR       (wr_pointer),
 
 
 
        .DI         (data_in),
 
 
 
        .DOUT       (data_out),
 
 
 
        .REN        (~fifo_selected),
 
 
 
        .WEN        (~(wr & (~fifo_full)))
 
 
 
    `ifdef PCI_BIST
 
 
 
        ,
 
 
 
        // debug chain signals
 
 
 
        .scanb_rst  (scanb_rst),
 
 
 
        .scanb_clk  (scanb_clk),
 
 
 
        .scanb_si   (scanb_si),
 
 
 
        .scanb_so   (scanb_s_0),
 
 
 
        .scanb_en   (scanb_en)
 
 
 
    `endif
 
 
 
    );
 
 
 
 
 
 
 
`ifdef PCI_BIST
 
 
 
    vs_hdtp_64x4_bist info_fifo
 
 
 
`else
 
 
 
    vs_hdtp_64x4 info_fifo
 
 
 
`endif
 
 
 
    (
 
 
 
        .RCK        (clk),
 
 
 
        .WCK        (clk),
 
 
 
        .RADR       (rd_info_pointer),
 
 
 
        .WADR       (wr_info_pointer),
 
 
 
        .DI         (len_cnt & {4{~initialize_memories}}),
 
 
 
        .DOUT       (length_info),
 
 
 
        .REN        (1'b0),
 
 
 
        .WEN        (~(write_length_info & (~info_full) | initialize_memories))
 
 
 
    `ifdef PCI_BIST
 
 
 
        ,
 
 
 
        // debug chain signals
 
 
 
        .scanb_rst  (scanb_rst),
 
 
 
        .scanb_clk  (scanb_clk),
 
 
 
        .scanb_si   (scanb_s_0),
 
 
 
        .scanb_so   (scanb_s_1),
 
 
 
        .scanb_en   (scanb_en)
 
 
 
    `endif
 
 
 
    );
 
 
 
 
 
 
 
`ifdef PCI_BIST
 
 
 
    vs_hdtp_64x1_bist overrun_fifo
 
 
 
`else
 
 
 
    vs_hdtp_64x1 overrun_fifo
 
 
 
`endif
 
 
 
    (
 
 
 
        .RCK        (clk),
 
 
 
        .WCK        (clk),
 
 
 
        .RADR       (rd_info_pointer),
 
 
 
        .WADR       (wr_info_pointer),
 
 
 
        .DI         ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
 
 
 
        .DOUT       (overrun),
 
 
 
        .REN        (1'b0),
 
 
 
        .WEN        (~(write_length_info & (~info_full) | initialize_memories))
 
 
 
    `ifdef PCI_BIST
 
 
 
        ,
 
 
 
        // debug chain signals
 
 
 
        .scanb_rst  (scanb_rst),
 
 
 
        .scanb_clk  (scanb_clk),
 
 
 
        .scanb_si   (scanb_s_1),
 
 
 
        .scanb_so   (scanb_so),
 
 
 
        .scanb_en   (scanb_en)
 
 
 
    `endif
 
 
 
    );
 
 
 
 
 
 
 
`else
 
  // writing data to fifo
 
  // writing data to fifo
 
  always @ (posedge clk)
 
  always @ (posedge clk)
 
  begin
 
  begin
 
    if (wr & (~fifo_full))
 
    if (wr & (~fifo_full))
 
      fifo[wr_pointer] <=#Tp data_in;
 
      fifo[wr_pointer] <=#Tp data_in;
Line 497... Line 599... 
  assign overrun = overrun_info[rd_info_pointer];
 
  assign overrun = overrun_info[rd_info_pointer];
 
 
 
 
 
 
 
 
 
`endif
 
`endif
 
`endif
 
`endif
 
 
 
`endif
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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