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Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.23 2003/04/15 15:31:24 mohor
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// Some features are supported in extended mode only (listen_only_mode...).
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//
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// Revision 1.22 2003/03/20 16:58:50 mohor
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// Revision 1.22 2003/03/20 16:58:50 mohor
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// unix.
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// unix.
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//
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//
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// Revision 1.20 2003/03/11 16:31:05 mohor
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// Revision 1.20 2003/03/11 16:31:05 mohor
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// Mux used for clkout to avoid "gated clocks warning".
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// Mux used for clkout to avoid "gated clocks warning".
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| Line 377... |
Line 380... |
reg node_bus_off_q;
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reg node_bus_off_q;
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reg node_error_passive_q;
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reg node_error_passive_q;
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reg transmit_buffer_status;
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reg transmit_buffer_status;
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reg single_shot_transmission;
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reg single_shot_transmission;
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reg [7:0] data_out_tmp;
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// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
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// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
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wire data_overrun_irq_en;
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wire data_overrun_irq_en;
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wire error_warning_irq_en;
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wire error_warning_irq_en;
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wire transmit_irq_en;
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wire transmit_irq_en;
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Line 1018... |
if(read) // read
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if(read) // read
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begin
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begin
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if (extended_mode) // EXTENDED mode (Different register map depends on mode)
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if (extended_mode) // EXTENDED mode (Different register map depends on mode)
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begin
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begin
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case(addr)
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case(addr)
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8'd0 : data_out_tmp <= {4'b0000, mode_ext[3:1], mode[0]};
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8'd0 : data_out <= {4'b0000, mode_ext[3:1], mode[0]};
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8'd1 : data_out_tmp <= 8'h0;
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8'd1 : data_out <= 8'h0;
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8'd2 : data_out_tmp <= status;
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8'd2 : data_out <= status;
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8'd3 : data_out_tmp <= irq_reg;
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8'd3 : data_out <= irq_reg;
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8'd4 : data_out_tmp <= irq_en_ext;
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8'd4 : data_out <= irq_en_ext;
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8'd6 : data_out_tmp <= bus_timing_0;
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8'd6 : data_out <= bus_timing_0;
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8'd7 : data_out_tmp <= bus_timing_1;
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8'd7 : data_out <= bus_timing_1;
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8'd11 : data_out_tmp <= {3'h0, arbitration_lost_capture[4:0]};
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8'd11 : data_out <= {3'h0, arbitration_lost_capture[4:0]};
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8'd12 : data_out_tmp <= error_capture_code;
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8'd12 : data_out <= error_capture_code;
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8'd13 : data_out_tmp <= error_warning_limit;
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8'd13 : data_out <= error_warning_limit;
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8'd14 : data_out_tmp <= rx_err_cnt;
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8'd14 : data_out <= rx_err_cnt;
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8'd15 : data_out_tmp <= tx_err_cnt;
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8'd15 : data_out <= tx_err_cnt;
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8'd16 : data_out_tmp <= acceptance_code_0;
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8'd16 : data_out <= acceptance_code_0;
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8'd17 : data_out_tmp <= acceptance_code_1;
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8'd17 : data_out <= acceptance_code_1;
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8'd18 : data_out_tmp <= acceptance_code_2;
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8'd18 : data_out <= acceptance_code_2;
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8'd19 : data_out_tmp <= acceptance_code_3;
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8'd19 : data_out <= acceptance_code_3;
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8'd20 : data_out_tmp <= acceptance_mask_0;
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8'd20 : data_out <= acceptance_mask_0;
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8'd21 : data_out_tmp <= acceptance_mask_1;
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8'd21 : data_out <= acceptance_mask_1;
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8'd22 : data_out_tmp <= acceptance_mask_2;
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8'd22 : data_out <= acceptance_mask_2;
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8'd23 : data_out_tmp <= acceptance_mask_3;
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8'd23 : data_out <= acceptance_mask_3;
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8'd24 : data_out_tmp <= 8'h0;
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8'd24 : data_out <= 8'h0;
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8'd25 : data_out_tmp <= 8'h0;
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8'd25 : data_out <= 8'h0;
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8'd26 : data_out_tmp <= 8'h0;
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8'd26 : data_out <= 8'h0;
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8'd27 : data_out_tmp <= 8'h0;
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8'd27 : data_out <= 8'h0;
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8'd28 : data_out_tmp <= 8'h0;
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8'd28 : data_out <= 8'h0;
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8'd29 : data_out_tmp <= {1'b0, rx_message_counter};
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8'd29 : data_out <= {1'b0, rx_message_counter};
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8'd31 : data_out_tmp <= clock_divider;
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8'd31 : data_out <= clock_divider;
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default: data_out_tmp <= 8'h0;
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default: data_out <= 8'h0;
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endcase
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endcase
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end
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end
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else // BASIC mode
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else // BASIC mode
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begin
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begin
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case(addr)
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case(addr)
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8'd0 : data_out_tmp <= {3'b001, mode_basic[4:1], mode[0]};
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8'd0 : data_out <= {3'b001, mode_basic[4:1], mode[0]};
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8'd1 : data_out_tmp <= 8'hff;
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8'd1 : data_out <= 8'hff;
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8'd2 : data_out_tmp <= status;
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8'd2 : data_out <= status;
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8'd3 : data_out_tmp <= {4'hf, irq_reg[3:0]};
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8'd3 : data_out <= {4'hf, irq_reg[3:0]};
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8'd4 : data_out_tmp <= reset_mode? acceptance_code_0 : 8'hff;
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8'd4 : data_out <= reset_mode? acceptance_code_0 : 8'hff;
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8'd5 : data_out_tmp <= reset_mode? acceptance_mask_0 : 8'hff;
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8'd5 : data_out <= reset_mode? acceptance_mask_0 : 8'hff;
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8'd6 : data_out_tmp <= reset_mode? bus_timing_0 : 8'hff;
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8'd6 : data_out <= reset_mode? bus_timing_0 : 8'hff;
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8'd7 : data_out_tmp <= reset_mode? bus_timing_1 : 8'hff;
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8'd7 : data_out <= reset_mode? bus_timing_1 : 8'hff;
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8'd10 : data_out_tmp <= reset_mode? 8'hff : tx_data_0;
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8'd10 : data_out <= reset_mode? 8'hff : tx_data_0;
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8'd11 : data_out_tmp <= reset_mode? 8'hff : tx_data_1;
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8'd11 : data_out <= reset_mode? 8'hff : tx_data_1;
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8'd12 : data_out_tmp <= reset_mode? 8'hff : tx_data_2;
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8'd12 : data_out <= reset_mode? 8'hff : tx_data_2;
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8'd13 : data_out_tmp <= reset_mode? 8'hff : tx_data_3;
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8'd13 : data_out <= reset_mode? 8'hff : tx_data_3;
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8'd14 : data_out_tmp <= reset_mode? 8'hff : tx_data_4;
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8'd14 : data_out <= reset_mode? 8'hff : tx_data_4;
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8'd15 : data_out_tmp <= reset_mode? 8'hff : tx_data_5;
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8'd15 : data_out <= reset_mode? 8'hff : tx_data_5;
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8'd16 : data_out_tmp <= reset_mode? 8'hff : tx_data_6;
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8'd16 : data_out <= reset_mode? 8'hff : tx_data_6;
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8'd17 : data_out_tmp <= reset_mode? 8'hff : tx_data_7;
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8'd17 : data_out <= reset_mode? 8'hff : tx_data_7;
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8'd18 : data_out_tmp <= reset_mode? 8'hff : tx_data_8;
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8'd18 : data_out <= reset_mode? 8'hff : tx_data_8;
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8'd19 : data_out_tmp <= reset_mode? 8'hff : tx_data_9;
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8'd19 : data_out <= reset_mode? 8'hff : tx_data_9;
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8'd31 : data_out_tmp <= clock_divider;
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8'd31 : data_out <= clock_divider;
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default: data_out_tmp <= 8'h0;
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default: data_out <= 8'h0;
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endcase
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endcase
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end
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end
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end
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end
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else
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else
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data_out_tmp <= 8'h0;
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data_out <= 8'h0;
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end
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end
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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data_out <= 0;
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else if (read)
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data_out <=#Tp data_out_tmp;
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end
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// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
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// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
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assign data_overrun_irq_en = extended_mode ? data_overrun_irq_en_ext : overrun_irq_en_basic;
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assign data_overrun_irq_en = extended_mode ? data_overrun_irq_en_ext : overrun_irq_en_basic;
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assign error_warning_irq_en = extended_mode ? error_warning_irq_en_ext : error_irq_en_basic;
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assign error_warning_irq_en = extended_mode ? error_warning_irq_en_ext : error_irq_en_basic;
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assign transmit_irq_en = extended_mode ? transmit_irq_en_ext : transmit_irq_en_basic;
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assign transmit_irq_en = extended_mode ? transmit_irq_en_ext : transmit_irq_en_basic;
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assign receive_irq_en = extended_mode ? receive_irq_en_ext : receive_irq_en_basic;
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assign receive_irq_en = extended_mode ? receive_irq_en_ext : receive_irq_en_basic;
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