URL
https://opencores.org/ocsvn/can/can/trunk
[/] [can/] [trunk/] [rtl/] [verilog/] [can_top.v] - Diff between revs 106 and 110
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 106 |
Rev 110 |
| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.41 2003/07/10 15:32:27 mohor
|
|
// Unused signal removed.
|
|
//
|
// Revision 1.40 2003/07/10 01:59:04 tadejm
|
// Revision 1.40 2003/07/10 01:59:04 tadejm
|
// Synchronization fixed. In some strange cases it didn't work according to
|
// Synchronization fixed. In some strange cases it didn't work according to
|
// the VHDL reference model.
|
// the VHDL reference model.
|
//
|
//
|
// Revision 1.39 2003/07/07 11:21:37 mohor
|
// Revision 1.39 2003/07/07 11:21:37 mohor
|
| Line 692... |
Line 695... |
|
|
// Multiplexing wb_dat_o from registers and rx fifo
|
// Multiplexing wb_dat_o from registers and rx fifo
|
always @ (extended_mode or addr or reset_mode)
|
always @ (extended_mode or addr or reset_mode)
|
begin
|
begin
|
if (extended_mode & (~reset_mode) & ((addr >= 8'd16) && (addr <= 8'd28)) | (~extended_mode) & ((addr >= 8'd20) && (addr <= 8'd29)))
|
if (extended_mode & (~reset_mode) & ((addr >= 8'd16) && (addr <= 8'd28)) | (~extended_mode) & ((addr >= 8'd20) && (addr <= 8'd29)))
|
data_out_fifo_selected <= 1'b1;
|
data_out_fifo_selected = 1'b1;
|
else
|
else
|
data_out_fifo_selected <= 1'b0;
|
data_out_fifo_selected = 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge clk_i)
|
always @ (posedge clk_i)
|
begin
|
begin
|
// if (wb_cyc_i & (~wb_we_i))
|
|
if (cs & (~we))
|
if (cs & (~we))
|
begin
|
begin
|
if (data_out_fifo_selected)
|
if (data_out_fifo_selected)
|
data_out <=#Tp data_out_fifo;
|
data_out <=#Tp data_out_fifo;
|
else
|
else
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.