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https://opencores.org/ocsvn/can/can/trunk
[/] [can/] [trunk/] [rtl/] [verilog/] [can_top.v] - Diff between revs 81 and 95
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| Rev 81 |
Rev 95 |
| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.36 2003/06/17 14:30:30 mohor
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// "chip select" signal cs_can_i is used only when not using WISHBONE
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// interface.
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//
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// Revision 1.35 2003/06/16 13:57:58 mohor
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// Revision 1.35 2003/06/16 13:57:58 mohor
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// tx_point generated one clk earlier. rx_i registered. Data corrected when
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// tx_point generated one clk earlier. rx_i registered. Data corrected when
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// using extended mode.
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// using extended mode.
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//
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//
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// Revision 1.34 2003/06/13 15:02:24 mohor
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// Revision 1.34 2003/06/13 15:02:24 mohor
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Line 655... |
/* End: Tx data registers */
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/* End: Tx data registers */
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/* Tx signal */
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/* Tx signal */
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.tx(tx_out),
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.tx(tx_out),
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.tx_oen(tx_oen)
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.tx_oen(tx_oen)
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`ifdef CAN_BIST
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,
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/* BIST signals */
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.scanb_rst(scanb_rst),
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.scanb_clk(scanb_clk),
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.scanb_si(scanb_si),
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.scanb_so(scanb_so),
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.scanb_en(scanb_en)
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`endif
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);
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);
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assign tx_o = tx_oen? 1'bz : tx_out;
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assign tx_o = tx_oen? 1'bz : tx_out;
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