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#-- Synplicity, Inc.
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#-- Synplicity, Inc.
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#-- Version 7.2
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#-- Version 7.2.2
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#-- Project file /projects/zoidberg/igorm/can/syn/synplicity/can.prj
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#-- Project file X:\zoidberg_soc\zoidberg_soc\can\syn\synplicity\can.prj
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#-- Written on Sat Mar 1 21:07:14 2003
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#-- Written on Tue Sep 23 14:15:42 2003
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#add_file options
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#add_file options
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add_file -verilog "$LIB/proasic/proasicplus.v"
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add_file -verilog "$LIB/proasic/proasicplus.v"
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add_file -verilog "../../../memory/actel/ram_64x8_sync/actel_ram_64x8_sync.v"
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add_file -verilog "../../../memory/actel/ram_64x8_sync/actel_ram_64x8_sync.v"
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project -result_file "rev_1/can_top.edn"
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project -result_file "rev_1/can_top.edn"
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#implementation attributes
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#implementation attributes
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set_option -compiler_compatible 0
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set_option -compiler_compatible 0
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set_option -include_path "../../rtl/verilog/;../../bench/verilog/"
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set_option -include_path "../../rtl/verilog/;../../bench/verilog/"
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impl -active "rev_1"
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#implementation: "rev_2"
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impl -add rev_2
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#device options
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set_option -technology PA
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set_option -part APA600
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set_option -speed_grade Std
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#compilation/mapping options
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set_option -default_enum_encoding default
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set_option -symbolic_fsm_compiler 1
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set_option -resource_sharing 0
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set_option -top_module "can_top"
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#map options
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set_option -frequency 50.000
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set_option -fanout_limit 12
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set_option -maxfan_hard 0
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set_option -disable_io_insertion 0
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set_option -report_path 4000
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#simulation options
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set_option -write_verilog 1
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set_option -write_vhdl 0
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#automatic place and route (vendor) options
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set_option -write_apr_constraint 1
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#set result format/file last
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project -result_file "rev_2/can_top.edn"
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#implementation attributes
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set_option -vlog_std v95
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set_option -compiler_compatible 0
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set_option -num_critical_paths ""
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set_option -num_startend_points ""
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set_option -include_path "../../rtl/verilog/;../../bench/verilog/"
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impl -active "rev_2"
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