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//////////////////////////////////////////////////////////////////////
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//// ////
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//// cavlc_fsm ////
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//// ////
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//// Description ////
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//// controls the cavlc parsing process ////
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//// ////
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//// Author(s): ////
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//// - bin qiu, qiubin@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2011 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//2011-8-7 18:57 initial revision
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//2011-8-7 18:57 initial revision
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`include "defines.v"
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`include "defines.v"
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module cavlc_fsm
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module cavlc_fsm
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//------------------------
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//------------------------
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//state & i & valid
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//state & i & valid
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//------------------------
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//------------------------
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always @(posedge clk or negedge rst_n)
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always @(posedge clk or negedge rst_n)
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if (~rst_n) begin
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if (!rst_n) begin
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state <= `cavlc_idle_s;
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state <= `cavlc_idle_s;
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i <= 0;
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i <= 0;
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valid <= 0;
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valid <= 0;
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end
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end
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else if (ena)
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else if (ena)
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state <= `cavlc_idle_s;
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state <= `cavlc_idle_s;
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valid <= 1;
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valid <= 1;
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end
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end
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end
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end
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`cavlc_read_t1s_flags_s : begin
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`cavlc_read_t1s_flags_s : begin
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if (TrailingOnes == TotalCoeff) //TotalCoeff should not be larger than max_coeff_num
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if (TrailingOnes == TotalCoeff)
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state <= `cavlc_read_total_zeros_s;
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state <= `cavlc_read_total_zeros_s;
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else begin
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else begin
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state <= `cavlc_read_level_prefix_s;
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state <= `cavlc_read_level_prefix_s;
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i <= i - TrailingOnes;
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i <= i - TrailingOnes;
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end
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end
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