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Subversion Repositories cfft

[/] [cfft/] [trunk/] [sim/] [tb_cfft1024x12_read_from_file.vhd] - Diff between revs 12 and 13

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Rev 12	Rev 13
Line 13...	Line 13...
`component cfft1024X12`	`component cfft1024X12`
`port(`	`port(`
`clk : in STD_LOGIC;`	`clk : in STD_LOGIC;`
`rst : in STD_LOGIC;`	`rst : in STD_LOGIC;`
`start : in STD_LOGIC;`	`start : in STD_LOGIC;`
`inv : in std_logic;`	`invert : in std_logic;`
`Iin : in STD_LOGIC_VECTOR(11 downto 0);`	`Iin : in STD_LOGIC_VECTOR(11 downto 0);`
`Qin : in STD_LOGIC_VECTOR(11 downto 0);`	`Qin : in STD_LOGIC_VECTOR(11 downto 0);`
`inputbusy : out STD_LOGIC;`	`inputbusy : out STD_LOGIC;`
`outdataen : out STD_LOGIC;`	`outdataen : out STD_LOGIC;`
`Iout : out STD_LOGIC_VECTOR(13 downto 0);`	`Iout : out STD_LOGIC_VECTOR(13 downto 0);`
Line 27...	Line 27...
`end component;`	`end component;`

`signal clk : STD_LOGIC;`	`signal clk : STD_LOGIC;`
`signal rst : STD_LOGIC;`	`signal rst : STD_LOGIC;`
`signal start : STD_LOGIC;`	`signal start : STD_LOGIC;`
`signal inv : std_logic;`	`signal invert : std_logic;`
`signal Iin : STD_LOGIC_VECTOR(11 downto 0);`	`signal Iin : STD_LOGIC_VECTOR(11 downto 0);`
`signal Qin : STD_LOGIC_VECTOR(11 downto 0);`	`signal Qin : STD_LOGIC_VECTOR(11 downto 0);`
`signal inputbusy : STD_LOGIC;`	`signal inputbusy : STD_LOGIC;`
`signal outdataen : STD_LOGIC;`	`signal outdataen : STD_LOGIC;`
`signal Iout : STD_LOGIC_VECTOR(13 downto 0);`	`signal Iout : STD_LOGIC_VECTOR(13 downto 0);`
Line 41...	Line 41...

`begin`	`begin`
`f: cfft1024x12 port map(clk=>clk,`	`f: cfft1024x12 port map(clk=>clk,`
`rst =>rst,`	`rst =>rst,`
`start=> start,`	`start=> start,`
`inv=>inv,`	`invert=>invert,`
`Iin=>Iin,`	`Iin=>Iin,`
`Qin=>Qin,`	`Qin=>Qin,`
`inputbusy=>inputbusy,`	`inputbusy=>inputbusy,`
`outdataen=>outdataen,`	`outdataen=>outdataen,`
`Iout=>Iout,`	`Iout=>Iout,`
Line 68...	Line 68...
`begin`	`begin`
`rst<='1';`	`rst<='1';`
`wait until clk'EVENT and clk='1';`	`wait until clk'EVENT and clk='1';`
`rst<='0';`	`rst<='0';`
`wait until clk'EVENT and clk='1';`	`wait until clk'EVENT and clk='1';`
`inv<='0';`	`invert<='0';`
`start<='1';`	`start<='1';`
`wait until clk'EVENT and clk='1';`	`wait until clk'EVENT and clk='1';`
`start<='0';`	`start<='0';`

`while not( endfile( FileIn1)) loop`	`while not( endfile( FileIn1)) loop`

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[/] [cfft/] [trunk/] [sim/] [tb_cfft1024x12_read_from_file.vhd] - Diff between revs 12 and 13