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Line 41... |
-- Modifier : ZHAO Ming
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-- Modifier : ZHAO Ming
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-- Desccription : modified fuction counter2address for syn
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-- Desccription : modified fuction counter2address for syn
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-- add rmask1,rmask2,wmask1,wmask2 signal
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-- add rmask1,rmask2,wmask1,wmask2 signal
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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-- Revisions : 0
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-- Revision Number : 3
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-- Version : 1.3.0
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-- Date : Nov 19 2002
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-- Modifier : ZHAO Ming
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-- Desccription : add output data position indication
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--
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--
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---------------------------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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Line 81... |
waddr : out STD_LOGIC_VECTOR(STAGE*2-1 downto 0);
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waddr : out STD_LOGIC_VECTOR(STAGE*2-1 downto 0);
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wen : out std_logic;
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wen : out std_logic;
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factorstart : out STD_LOGIC;
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factorstart : out STD_LOGIC;
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cfft4start : out STD_LOGIC;
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cfft4start : out STD_LOGIC;
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outdataen : out std_logic;
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outdataen : out std_logic;
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inputbusy : out std_logic
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inputbusy : out std_logic;
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OutPosition : out STD_LOGIC_VECTOR( 2*STAGE-1 downto 0 )
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);
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);
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end address;
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end address;
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architecture address of address is
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architecture address of address is
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end if;
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end if;
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end loop;
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end loop;
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return result;
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return result;
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end counter2addr;
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end counter2addr;
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function outcounter2addr(
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counter : std_logic_vector
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) return std_logic_vector is
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variable result :std_logic_vector(counter'range);
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begin
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for n in 0 to STAGE-1 loop
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result( 2*n+1 downto 2*n ):=counter( counter'high-2*n downto counter'high-2*n-1 );
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end loop;
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return result;
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end outcounter2addr;
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signal rstate,wstate,state:std_logic_vector( 3 downto 0 );
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signal rstate,wstate,state:std_logic_vector( 3 downto 0 );
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signal rmask1,rmask2,wmask1,wmask2:std_logic_vector( STAGE-1 downto 0 );
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signal rmask1,rmask2,wmask1,wmask2:std_logic_vector( STAGE-1 downto 0 );
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signal counter,wcounter,rcounter:std_logic_vector( STAGE*2-1 downto 0 );
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signal counter,wcounter,rcounter:std_logic_vector( STAGE*2-1 downto 0 );
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signal outcounter:std_logic_vector( STAGE*2 downto 0 );
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signal outcounter:std_logic_vector( STAGE*2 downto 0 );
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Line 150... |
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begin
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begin
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outdataen<=outcounter(STAGE*2);
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outdataen<=outcounter(STAGE*2);
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OutPosition<=outcounter2addr( outcounter( STAGE*2-1 downto 0 ));
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count:process( clk, rst )
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count:process( clk, rst )
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begin
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begin
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if rst='1' then
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if rst='1' then
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counter<=( others=>'0' );
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counter<=( others=>'0' );
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state<=CONV_STD_LOGIC_VECTOR( STAGE+1,4);
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state<=CONV_STD_LOGIC_VECTOR( STAGE+1,4);
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