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https://opencores.org/ocsvn/cfft/cfft/trunk
[/] [cfft/] [trunk/] [src/] [cfft4.vhd] - Diff between revs 2 and 13
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| Rev 2 |
Rev 13 |
| Line 37... |
Line 37... |
);
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);
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port(
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port(
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clk : in STD_LOGIC;
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clk : in STD_LOGIC;
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rst : in STD_LOGIC;
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rst : in STD_LOGIC;
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start : in STD_LOGIC;
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start : in STD_LOGIC;
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inv : in std_logic;
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invert : in std_logic;
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I : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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I : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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Q : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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Q : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
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Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
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Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0)
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Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0)
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);
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);
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| Line 94... |
Line 94... |
Qout<=SXT(RegBQ(1),WIDTH+2)-SXT(RegBQ(3),WIDTH+2);
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Qout<=SXT(RegBQ(1),WIDTH+2)-SXT(RegBQ(3),WIDTH+2);
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--1 rA(1)<=A1 rB(3)<=(-j)*(rA(1)-rA(3)) B0<=rB(0)+rB(2)--
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--1 rA(1)<=A1 rB(3)<=(-j)*(rA(1)-rA(3)) B0<=rB(0)+rB(2)--
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when "01" =>
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when "01" =>
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RegAI(1)<=I;
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RegAI(1)<=I;
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RegAQ(1)<=Q;
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RegAQ(1)<=Q;
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if inv='0' then
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if invert='0' then
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-- for fft *(-j)
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-- for fft *(-j)
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RegBI(3)<=SXT(RegAQ(1),WIDTH+1)-SXT(RegAQ(3),WIDTH+1);
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RegBI(3)<=SXT(RegAQ(1),WIDTH+1)-SXT(RegAQ(3),WIDTH+1);
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RegBQ(3)<=SXT(RegAI(3),WIDTH+1)-SXT(RegAI(1),WIDTH+1);
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RegBQ(3)<=SXT(RegAI(3),WIDTH+1)-SXT(RegAI(1),WIDTH+1);
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else
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else
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-- for fft *(j)
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-- for fft *(j)
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