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https://opencores.org/ocsvn/cic_core_2/cic_core_2/trunk
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Rev 9 |
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input clk,
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input clk,
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input reset_n,
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input reset_n,
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input clear,
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input clear,
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input wire signed [DATA_WIDTH_INP - 1:0] inp_samp_data,
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input wire signed [DATA_WIDTH_INP - 1:0] inp_samp_data,
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input inp_samp_str,
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input inp_samp_str,
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output reg signed [DATA_WIDTH_OUT - 1:0] out_samp_data
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output wire signed [DATA_WIDTH_OUT - 1:0] out_samp_data
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);
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);
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/*********************************************************************************************/
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/*********************************************************************************************/
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wire signed [DATA_WIDTH_OUT - 1:0] sum;
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localparam SUMMER_WIDTH = DATA_WIDTH_INP > DATA_WIDTH_OUT ? DATA_WIDTH_INP : DATA_WIDTH_OUT;
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assign #4 sum = out_samp_data + inp_samp_data; // delay for 18x18 multiplier of Cyclone V SE is 3.4 ns
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wire signed [SUMMER_WIDTH - 1:0] sum;
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reg signed [SUMMER_WIDTH - 1:0] acc_reg;
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assign #4 sum = acc_reg + inp_samp_data; // delay for 18x18 multiplier of Cyclone V SE is 3.4 ns
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always @(posedge clk or negedge reset_n)
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always @(posedge clk or negedge reset_n)
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begin
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begin
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if (!reset_n) out_samp_data <= '0;
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if (!reset_n) acc_reg <= '0;
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else if (clear) out_samp_data <= '0;
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else if (clear) acc_reg <= '0;
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else if (inp_samp_str) out_samp_data <= sum;
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else if (inp_samp_str) acc_reg <= sum;
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end
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end
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assign out_samp_data = acc_reg[SUMMER_WIDTH - 1 -: DATA_WIDTH_OUT];
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/*********************************************************************************************/
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/*********************************************************************************************/
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endmodule
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endmodule
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