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//------------------------------------------------------------------------
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// This Verilog file was developed by Altera Corporation. It may be
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// freely copied and/or distributed at no cost. Any persons using this
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// file for any purpose do so at their own risk, and are responsible for
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// the results of such use. Altera Corporation does not guarantee that
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// this file is complete, correct, or fit for any particular purpose.
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// NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must
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// accompany any copy of this file.
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//
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//------------------------------------------------------------------------
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// Imported to Opencores directory. Date Sept 10, 2001
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// Split related modules into separate files, as the manual splits them.
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// Added example instantiations to the beginning of each file.
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//
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/* EXAMPLE INSTANTIATIONS:
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lpm_constant
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#( 1, // lpm_width
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0, // lpm_cvalue
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"UNUSED" // lpm_strength, optional, {UNUSED, WEAK}
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) lpm_constant_example (
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.result (const_out[lpm_width-1:0])
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);
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lpm_inv
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#( 1 // lpm_width
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) lpm_inv_example (
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.result (data_out[lpm_width-1:0]),
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.data (data_in[lpm_width-1:0])
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);
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// NOTE: Bits data[lpm_size-1:0] are ANDed together to make result[0]
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lpm_and
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#( 1, // lpm_width (output width)
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1 // lpm_size (inputs to each gate)
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) lpm_and_example (
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.result (data_out[lpm_width-1:0]),
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.data (data_in[(lpm_size*lpm_width)-1:0])
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);
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// NOTE: Bits data[lpm_size-1:0] are ORed together to make result[0]
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lpm_or
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#( 1, // lpm_width (output width)
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1 // lpm_size (inputs to each gate)
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) lpm_or_example (
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.result (data_out[lpm_width-1:0]),
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.data (data_in[(lpm_size*lpm_width)-1:0])
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);
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// NOTE: Bits data_[lpm_size-1:0] are XORed together to make result[0]
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lpm_xor
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#( 1, // lpm_width (output width)
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1 // lpm_size (inputs to each gate)
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) lpm_xor_example (
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.result (data_out[lpm_width-1:0]),
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.data (data_in[(lpm_size*lpm_width)-1:0])
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);
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lpm_bustri
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#( 1 // lpm_width
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) lpm_bustri_example (
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.tridata (data_tristate[lpm_width-1:0]),
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.data (data_to_tristate[lpm_width-1:0]), // CHOICE
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.enabledt (enable_data_to_tristate_bus_HIGH), // OPTIONAL
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.result (data_from_tristate[lpm_width-1:0]), // CHOICE
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.enabletr (enable_data_to_result_bus_HIGH), // OPTIONAL
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);
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// NOTE: Bits data[lpm_size-1:0] are SELECTED to make result[0]
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lpm_mux
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#( 1, // lpm_width (output width)
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1, // lpm_size (inputs to each mux)
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1, // lpm_widths (number of bits in output select bus)
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0 // lpm_pipeline, optional, {0, 1}
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) lpm_mux_example (
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.result (data_out[lpm_width-1:0]),
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.data (data_in[(lpm_size*lpm_width)-1:0]),
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.sel (data_sel[lpm_widths-1:0]),
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.clock (clock_if_pipelined), // OPTIONAL
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.clken (clock_enable_HIGH_if_pipelined), // OPTIONAL
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.aclr (async_clear_if_pipelined) // OPTIONAL
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);
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lpm_decode
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#( 1, // lpm_width (number of bits in input to be decoded)
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1, // lpm_decodes (number of actual outputs decoded)
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0 // lpm_pipeline, optional, {0, 1}
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) lpm_decode_example (
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.eq (decodes_out[lpm_decodes-1:0]),
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.data (data_in[lpm_width:0]),
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.enable (force_all_outputs_LOW_when_LOW), // OPTIONAL
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.clock (clock_if_pipelined), // OPTIONAL
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.clken (clock_enable_HIGH_if_pipelined), // OPTIONAL
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.aclr (async_clear_if_pipelined) // OPTIONAL
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);
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lpm_clshift
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#( 1, // lpm_width (width of input vector)
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1, // lpm_widthdist (width of shift distance port)
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"LOGICAL" // lpm_shifttype, optional, {LOGICAL, ROTATE, ARITHMETIC}
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) lpm_clshift_example (
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.result (data_out[lpm_width-1:0]),
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.overflow (overflow_means_arith_bit_lost_or_result_became_0), // OPTIONAL
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.underflow (underflow_means_result_became_0), // OPTIONAL
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.data (data_in[lpm_width-1:0]),
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.direction (low_means_towards_LSB), // OPTIONAL
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.distance (shift_distance[lpm_widthdist-1:0])
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);
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*/
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//------------------------------------------------------------------------
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// LPM Synthesizable Models
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//------------------------------------------------------------------------
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// Version 1.5 (lpm 220) Date 12/17/99
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//
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// Modified LPM_ADD_SUB and LPM_MULT to accomodate LPM_WIDTH = 1.
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// Default values for LPM_WIDTH* are changed back to 1.
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// Added LPM_HINT to LPM_DIVIDE.
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// Rewritten LPM_FIFO_DC to output correctly.
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// Modified LPM_FIFO to output 0s before first read, output correct
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// values after aclr and sclr, and output LPM_NUMWORDS mod
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// exp(2, LPM_WIDTHU) when FIFO is full.
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//
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//------------------------------------------------------------------------
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// Version 1.4.1 (lpm 220) Date 10/29/99
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//
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// Default values for LPM_WIDTH* of LPM_ADD_SUB and LPM_MULT are changed
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// from 1 to 2.
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//
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//------------------------------------------------------------------------
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// Version 1.4 (lpm 220) Date 10/18/99
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//
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// Default values for each optional inputs for ALL modules are added.
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// Some LPM_PVALUE implementations were missing, and now implemented.
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//
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//------------------------------------------------------------------------
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// Version 1.3 (lpm 220) Date 06/23/99
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//
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// Corrected LPM_FIFO and LPM_FIFO_DC cout and empty/full flags.
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// Implemented LPM_COUNTER cin/cout, and LPM_MODULUS is now working.
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//
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//------------------------------------------------------------------------
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// Version 1.2 (lpm 220) Date 06/16/99
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//
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// Added LPM_RAM_DP, LPM_RAM_DQ, LPM_IO, LPM_ROM, LPM_FIFO, LPM_FIFO_DC.
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// Parameters and ports are added/discarded according to the spec.
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//
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//------------------------------------------------------------------------
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// Version 1.1 (lpm 220) Date 02/05/99
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//
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// Added LPM_DIVIDE module.
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//
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//------------------------------------------------------------------------
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// Version 1.0 Date 07/09/97
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//
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//------------------------------------------------------------------------
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// Excluded Functions:
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//
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// LPM_FSM and LPM_TTABLE.
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//
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//------------------------------------------------------------------------
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// Assumptions:
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//
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// 1. LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, and LPM_NUMWORDS,
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// LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE default value is
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// string UNUSED.
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//
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//------------------------------------------------------------------------
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// Verilog Language Issues:
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//
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// Two dimensional ports are not supported. Modules with two dimensional
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// ports are implemented as one dimensional signal of (LPM_SIZE * LPM_WIDTH)
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// bits wide.
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//
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//------------------------------------------------------------------------
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// Synthesis Issues:
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//
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// 1. LPM_COUNTER
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//
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// Currently synthesis tools do not allow mixing of level and edge
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// sensetive signals. To overcome that problem the "data" signal is
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// removed from the clock always block of lpm_counter, however the
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// synthesis result is accurate. For correct simulation add the "data"
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// pin to the sensetivity list as follows:
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//
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// always @(posedge clock or posedge aclr or posedge aset or
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// posedge aload or data)
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//------------------------------------------------------------------------
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module lpm_constant ( result );
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// NOTE: Parameters must be declared in the same order as the Properties
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// are specified in the Cell Specification document.
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parameter lpm_width = 1;
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parameter lpm_cvalue = 0;
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parameter lpm_strength = "UNUSED";
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parameter lpm_type = "lpm_constant";
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parameter lpm_hint = "UNUSED";
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parameter lpm_source_version = "lpm 220 version 1.6";
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output [lpm_width-1:0] result;
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assign result = lpm_cvalue;
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// Check for previous Parameter declaration order
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initial if ((lpm_width === "lpm_constant") || (lpm_type !== "lpm_constant"))
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begin
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$display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
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$finish;
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end
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endmodule // lpm_constant
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//------------------------------------------------------------------------
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module lpm_inv ( result, data );
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// NOTE: Parameters must be declared in the same order as the Properties
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// are specified in the Cell Specification document.
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parameter lpm_width = 1;
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parameter lpm_type = "lpm_inv";
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parameter lpm_hint = "UNUSED";
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parameter lpm_source_version = "lpm 220 version 1.6";
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input [lpm_width-1:0] data;
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output [lpm_width-1:0] result;
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reg [lpm_width-1:0] result;
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always @(data)
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begin
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result = ~data;
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end
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// Check for previous Parameter declaration order
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initial if ((lpm_width === "lpm_inv") || (lpm_type !== "lpm_inv"))
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begin
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$display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
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$finish;
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end
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endmodule // lpm_inv
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//------------------------------------------------------------------------
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module lpm_and ( result, data );
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// NOTE: Parameters must be declared in the same order as the Properties
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// are specified in the Cell Specification document.
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parameter lpm_width = 1;
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parameter lpm_size = 1;
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parameter lpm_type = "lpm_and";
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parameter lpm_hint = "UNUSED";
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parameter lpm_source_version = "lpm 220 version 1.6";
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input [(lpm_size * lpm_width)-1:0] data;
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output [lpm_width-1:0] result;
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reg [lpm_width-1:0] result;
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integer i, j, k;
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always @(data)
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begin
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for (i=0; i<lpm_width; i=i+1)
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begin
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result[i] = data[i];
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for (j=1; j<lpm_size; j=j+1)
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begin
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k = j * lpm_width + i;
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result[i] = result[i] & data[k];
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end
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end
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end
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// Check for previous Parameter declaration order
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initial if ((lpm_width === "lpm_and") || (lpm_type !== "lpm_and"))
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begin
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$display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
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$finish;
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end
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endmodule // lpm_and
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//------------------------------------------------------------------------
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module lpm_or ( result, data );
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// NOTE: Parameters must be declared in the same order as the Properties
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// are specified in the Cell Specification document.
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parameter lpm_width = 1;
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parameter lpm_size = 1;
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parameter lpm_type = "lpm_or";
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parameter lpm_hint = "UNUSED";
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parameter lpm_source_version = "lpm 220 version 1.6";
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input [(lpm_size * lpm_width)-1:0] data;
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output [lpm_width-1:0] result;
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reg [lpm_width-1:0] result;
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integer i, j, k;
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always @(data)
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begin
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for (i=0; i<lpm_width; i=i+1)
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begin
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result[i] = data[i];
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for (j=1; j<lpm_size; j=j+1)
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begin
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k = j * lpm_width + i;
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result[i] = result[i] | data[k];
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end
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end
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end
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// Check for previous Parameter declaration order
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initial if ((lpm_width === "lpm_or") || (lpm_type !== "lpm_or"))
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begin
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$display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
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$finish;
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end
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endmodule // lpm_or
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//------------------------------------------------------------------------
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module lpm_xor ( result, data );
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// NOTE: Parameters must be declared in the same order as the Properties
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// are specified in the Cell Specification document.
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parameter lpm_width = 1;
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parameter lpm_size = 1;
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parameter lpm_type = "lpm_xor";
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parameter lpm_hint = "UNUSED";
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parameter lpm_source_version = "lpm 220 version 1.6";
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input [(lpm_size * lpm_width)-1:0] data;
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output [lpm_width-1:0] result;
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reg [lpm_width-1:0] result;
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integer i, j, k;
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always @(data)
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begin
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for (i=0; i<lpm_width; i=i+1)
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begin
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result[i] = data[i];
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for (j=1; j<lpm_size; j=j+1)
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begin
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k = j * lpm_width + i;
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result[i] = result[i] ^ data[k];
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end
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end
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end
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// Check for previous Parameter declaration order
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initial if ((lpm_width === "lpm_xor") || (lpm_type !== "lpm_xor"))
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begin
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$display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
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$finish;
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end
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endmodule // lpm_xor
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//------------------------------------------------------------------------
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module lpm_bustri ( result, tridata, data, enabledt, enabletr );
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// NOTE: Parameters must be declared in the same order as the Properties
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// are specified in the Cell Specification document.
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parameter lpm_width = 1;
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parameter lpm_type = "lpm_bustri";
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parameter lpm_hint = "UNUSED";
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parameter lpm_source_version = "lpm 220 version 1.6";
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input [lpm_width-1:0] data;
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input enabledt;
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input enabletr;
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output [lpm_width-1:0] result;
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inout [lpm_width-1:0] tridata;
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reg [lpm_width-1:0] result;
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reg [lpm_width-1:0] tmp_tridata;
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tri0 enabledt;
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tri0 enabletr;
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buf (i_enabledt, enabledt);
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buf (i_enabletr, enabletr);
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always @(data or tridata or i_enabletr or i_enabledt)
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begin
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if (i_enabledt == 0 && i_enabletr == 1)
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begin
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result = tridata;
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tmp_tridata = 'bz;
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end
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else if (i_enabledt == 1 && i_enabletr == 0)
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begin
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result = 'bz;
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tmp_tridata = data;
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end
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else if (i_enabledt == 1 && i_enabletr == 1)
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begin
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result = data;
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tmp_tridata = data;
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end
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else
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begin
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result = 'bz;
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tmp_tridata = 'bz;
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end
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end
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assign tridata = tmp_tridata;
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// Check for previous Parameter declaration order
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initial if ((lpm_width === "lpm_bustri") || (lpm_type !== "lpm_bustri"))
|
|
begin
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|
$display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
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$finish;
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end
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endmodule // lpm_bustri
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//------------------------------------------------------------------------
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module lpm_mux ( result, clock, clken, data, aclr, sel );
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|
|
|
// NOTE: Parameters must be declared in the same order as the Properties
|
|
// are specified in the Cell Specification document.
|
|
parameter lpm_width = 1;
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parameter lpm_size = 1;
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parameter lpm_widths = 1;
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parameter lpm_pipeline = 0;
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parameter lpm_type = "lpm_mux";
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parameter lpm_hint = "UNUSED";
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parameter lpm_source_version = "lpm 220 version 1.6";
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input [(lpm_size * lpm_width)-1:0] data;
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input aclr;
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input clock;
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input clken;
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input [lpm_widths-1:0] sel;
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output [lpm_width-1:0] result;
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integer i, j, m, n;
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reg [lpm_width-1:0] tmp_result;
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reg [lpm_width-1:0] tmp_result2 [lpm_pipeline:0];
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tri0 aclr;
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tri0 clock;
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tri1 clken;
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buf (i_aclr, aclr);
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buf (i_clock, clock);
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buf (i_clken, clken);
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always @(data or sel)
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begin
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tmp_result = 0;
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for (m=0; m<lpm_width; m=m+1)
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begin
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n = sel * lpm_width + m;
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tmp_result[m] = data[n];
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end
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end
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always @(posedge i_clock or posedge i_aclr)
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begin
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if (i_aclr)
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begin
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for (i = 0; i <= lpm_pipeline; i = i + 1)
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tmp_result2[i] = 'b0;
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|
end
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else if (i_clken == 1)
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|
begin
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tmp_result2[lpm_pipeline] = tmp_result;
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for (j = 0; j < lpm_pipeline; j = j +1)
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tmp_result2[j] = tmp_result2[j+1];
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end
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end
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assign result = (lpm_pipeline > 0) ? tmp_result2[0] : tmp_result;
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|
|
// Check for previous Parameter declaration order
|
|
initial if ((lpm_width === "lpm_mux") || (lpm_type !== "lpm_mux"))
|
|
begin
|
|
$display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
|
|
$finish;
|
|
end
|
|
endmodule // lpm_mux
|
|
|
|
//------------------------------------------------------------------------
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|
|
|
module lpm_decode ( eq, data, enable, clock, clken, aclr );
|
|
|
|
// NOTE: Parameters must be declared in the same order as the Properties
|
|
// are specified in the Cell Specification document.
|
|
parameter lpm_width = 1;
|
|
parameter lpm_decodes = 1 << lpm_width;
|
|
parameter lpm_pipeline = 0;
|
|
parameter lpm_type = "lpm_decode";
|
|
parameter lpm_hint = "UNUSED";
|
|
parameter lpm_source_version = "lpm 220 version 1.6";
|
|
|
|
input [lpm_width-1:0] data;
|
|
input enable;
|
|
input clock;
|
|
input clken;
|
|
input aclr;
|
|
output [lpm_decodes-1:0] eq;
|
|
|
|
reg [lpm_decodes-1:0] tmp_eq2 [lpm_pipeline:0];
|
|
reg [lpm_decodes-1:0] tmp_eq;
|
|
integer i, j;
|
|
|
|
tri0 clock;
|
|
tri1 clken;
|
|
tri0 aclr;
|
|
tri1 enable;
|
|
|
|
buf (i_clock, clock);
|
|
buf (i_clken, clken);
|
|
buf (i_aclr, aclr);
|
|
buf (i_enable, enable);
|
|
|
|
|
|
always @(data or i_enable)
|
|
begin
|
|
tmp_eq = 0;
|
|
if (i_enable)
|
|
begin
|
|
if ((data < lpm_decodes))
|
|
begin
|
|
tmp_eq[data] = 1'b1;
|
|
end
|
|
else
|
|
tmp_eq = 0;
|
|
end
|
|
end
|
|
|
|
always @(posedge i_clock or posedge i_aclr)
|
|
begin
|
|
if (i_aclr)
|
|
begin
|
|
for (i = 0; i <= lpm_pipeline; i = i + 1)
|
|
tmp_eq2[i] = 'b0;
|
|
end
|
|
else if (clken == 1)
|
|
begin
|
|
tmp_eq2[lpm_pipeline] = tmp_eq;
|
|
for (j = 0; j < lpm_pipeline; j = j +1)
|
|
tmp_eq2[j] = tmp_eq2[j+1];
|
|
end
|
|
end
|
|
|
|
assign eq = (lpm_pipeline > 0) ? tmp_eq2[0] : tmp_eq;
|
|
|
|
// Check for previous Parameter declaration order
|
|
initial if ((lpm_width === "lpm_decode") || (lpm_type !== "lpm_decode"))
|
|
begin
|
|
$display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
|
|
$finish;
|
|
end
|
|
endmodule // lpm_decode
|
|
|
|
//------------------------------------------------------------------------
|
|
|
|
module lpm_clshift ( result, overflow, underflow, data, direction, distance );
|
|
|
|
// NOTE: Parameters must be declared in the same order as the Properties
|
|
// are specified in the Cell Specification document.
|
|
parameter lpm_width = 1;
|
|
parameter lpm_widthdist = 1;
|
|
parameter lpm_shifttype = "LOGICAL";
|
|
parameter lpm_type = "lpm_clshift";
|
|
parameter lpm_hint = "UNUSED";
|
|
parameter lpm_source_version = "lpm 220 version 1.6";
|
|
|
|
input [lpm_width-1:0] data;
|
|
input [lpm_widthdist-1:0] distance;
|
|
input direction;
|
|
output [lpm_width-1:0] result;
|
|
output overflow;
|
|
output underflow;
|
|
|
|
reg [lpm_width-1:0] ONES;
|
|
reg [lpm_width-1:0] result;
|
|
reg overflow, underflow;
|
|
integer i;
|
|
|
|
tri0 direction;
|
|
|
|
buf (i_direction, direction);
|
|
|
|
//---------------------------------------------------------------//
|
|
function [lpm_width+1:0] LogicShift;
|
|
input [lpm_width-1:0] data;
|
|
input [lpm_widthdist-1:0] dist;
|
|
input direction;
|
|
reg [lpm_width-1:0] tmp_buf;
|
|
reg overflow, underflow;
|
|
|
|
begin
|
|
tmp_buf = data;
|
|
overflow = 1'b0;
|
|
underflow = 1'b0;
|
|
if ((direction) && (dist > 0)) // shift right
|
|
begin
|
|
tmp_buf = data >> dist;
|
|
if ((data != 0) && ((dist >= lpm_width) || (tmp_buf == 0)))
|
|
underflow = 1'b1;
|
|
end
|
|
else if (dist > 0) // shift left
|
|
begin
|
|
tmp_buf = data << dist;
|
|
if ((data != 0) && ((dist >= lpm_width)
|
|
|| ((data >> (lpm_width-dist)) != 0)))
|
|
overflow = 1'b1;
|
|
end
|
|
LogicShift = {overflow,underflow,tmp_buf[lpm_width-1:0]};
|
|
end
|
|
endfunction
|
|
|
|
//---------------------------------------------------------------//
|
|
function [lpm_width+1:0] ArithShift;
|
|
input [lpm_width-1:0] data;
|
|
input [lpm_widthdist-1:0] dist;
|
|
input direction;
|
|
reg [lpm_width-1:0] tmp_buf;
|
|
reg overflow, underflow;
|
|
|
|
begin
|
|
tmp_buf = data;
|
|
overflow = 1'b0;
|
|
underflow = 1'b0;
|
|
|
|
if (direction && (dist > 0)) // shift right
|
|
begin
|
|
if (data[lpm_width-1] == 0) // positive number
|
|
begin
|
|
tmp_buf = data >> dist;
|
|
if ((data != 0) && ((dist >= lpm_width) || (tmp_buf == 0)))
|
|
underflow = 1'b1;
|
|
end
|
|
else // negative number
|
|
begin
|
|
tmp_buf = (data >> dist) | (ONES << (lpm_width - dist));
|
|
if ((data != ONES) && ((dist >= lpm_width-1) || (tmp_buf == ONES)))
|
|
underflow = 1'b1;
|
|
end
|
|
end
|
|
else if (dist > 0) // shift left
|
|
begin
|
|
tmp_buf = data << dist;
|
|
if (data[lpm_width-1] == 0) // positive number
|
|
begin
|
|
if ((data != 0) && ((dist >= lpm_width-1)
|
|
|| ((data >> (lpm_width-dist-1)) != 0)))
|
|
overflow = 1'b1;
|
|
end
|
|
else // negative number
|
|
begin
|
|
if ((data != ONES) && ((dist >= lpm_width)
|
|
|| (((data >> (lpm_width-dist-1))|(ONES << (dist+1))) != ONES)))
|
|
overflow = 1'b1;
|
|
end
|
|
end
|
|
ArithShift = {overflow,underflow,tmp_buf[lpm_width-1:0]};
|
|
end
|
|
endfunction
|
|
|
|
//---------------------------------------------------------------//
|
|
function [lpm_width-1:0] RotateShift;
|
|
input [lpm_width-1:0] data;
|
|
input [lpm_widthdist-1:0] dist;
|
|
input direction;
|
|
reg [lpm_width-1:0] tmp_buf;
|
|
|
|
begin
|
|
tmp_buf = data;
|
|
if ((direction) && (dist > 0)) // shift right
|
|
begin
|
|
tmp_buf = (data >> dist) | (data << (lpm_width - dist));
|
|
end
|
|
else if (dist > 0) // shift left
|
|
begin
|
|
tmp_buf = (data << dist) | (data >> (lpm_width - dist));
|
|
end
|
|
RotateShift = tmp_buf[lpm_width-1:0];
|
|
end
|
|
endfunction
|
|
//---------------------------------------------------------------//
|
|
|
|
initial
|
|
begin
|
|
for (i=0; i < lpm_width; i=i+1)
|
|
ONES[i] = 1'b1;
|
|
end
|
|
|
|
always @(data or i_direction or distance)
|
|
begin
|
|
// lpm_shifttype is optional and default to LOGICAL
|
|
if ((lpm_shifttype == "LOGICAL"))
|
|
begin
|
|
{overflow,underflow,result} = LogicShift(data,distance,i_direction);
|
|
end
|
|
else if (lpm_shifttype == "ARITHMETIC")
|
|
begin
|
|
{overflow,underflow,result} = ArithShift(data,distance,i_direction);
|
|
end
|
|
else if (lpm_shifttype == "ROTATE")
|
|
begin
|
|
result = RotateShift(data, distance, i_direction);
|
|
overflow = 1'b0;
|
|
underflow = 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
result = 'bx;
|
|
overflow = 1'b0;
|
|
underflow = 1'b0;
|
|
end
|
|
end
|
|
|
|
// Check for previous Parameter declaration order
|
|
initial if ((lpm_width === "lpm_clshift") || (lpm_type !== "lpm_clshift"))
|
|
begin
|
|
$display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
|
|
$finish;
|
|
end
|
|
endmodule // lpm_clshift
|
|
|
No newline at end of file
|
No newline at end of file
|
