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//------------------------------------------------------------------------
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// This Verilog file was developed by Altera Corporation. It may be
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// freely copied and/or distributed at no cost. Any persons using this
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// file for any purpose do so at their own risk, and are responsible for
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// the results of such use. Altera Corporation does not guarantee that
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// this file is complete, correct, or fit for any particular purpose.
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// NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must
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// accompany any copy of this file.
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//
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//------------------------------------------------------------------------
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// Imported to Opencores directory. Date Sept 10, 2001
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// Split related modules into separate files, as the manual splits them.
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// Added example instantiations to the beginning of each file.
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//
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/* EXAMPLE INSTANTIATIONS:
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lpm_latch
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#( 1, // lpm_width
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"UNUSED", // lpm_avalue, aset value, optional, -1 if not set
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"UNUSED" // lpm_pvalue, power-up value, optional
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) lpm_latch_example (
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.q (data_out[lpm_width-1:0]),
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.data (data_in[lpm_width-1:0]),
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.gate (pass_thru_when_HIGH),
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.aset (set_to_aset_value_when_HIGH), // OPTIONAL
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.aclr (set_to_zero_when_HIGH) // OPTIONAL
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);
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lpm_ff
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#( 1, // lpm_width
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"UNUSED", // lpm_avalue, aset value, optional, -1 if not set
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"UNUSED", // lpm_svalue, sset value, optional, -1 if not set
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"UNUSED", // lpm_pvalue, power-up value, optional
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"DFF" // lpm_fftype, optional, {DFF, TFF}
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) lpm_ff_example (
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.q (data_out[lpm_width-1:0]),
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.data (data_in[lpm_width-1:0]),
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.clock (rising_edge_flop_clock),
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.enable (clock_enable_when_HIGH), // OPTIONAL
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.sload (load_data_to_toggle_flops_if_TFF), // OPTIONAL
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.sset (load_data_from_svalue_if_HIGH), // OPTIONAL
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.sclr (set_value_to_0_if_HIGH), // OPTIONAL
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.aload (load_data_to_toggle_flops_if_TFF), // OPTIONAL
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.aset (load_data_from_svalue_if_HIGH), // OPTIONAL
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.aclr (set_value_to_0_if_HIGH) // OPTIONAL
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);
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lpm_shiftreg
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#( 1, // lpm_width
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"UNUSED", // lpm_avalue, aset value, optional, -1 if not set
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"UNUSED", // lpm_svalue, sset value, optional, -1 if not set
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"UNUSED", // lpm_pvalue, power-up value, optional
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"LEFT" // lpm_direction, optional, {LEFT, RIGHT}
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) lpm_shiftreg_example (
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.q (data_out[lpm_width-1:0]),
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.shiftout (shift_data_from_LSB_or_MSB),
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.data (parallel_data_in[lpm_width-1:0]), // OPTIONAL
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.shiftin (shift_data_to_LSB_or_MSB),
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.clock (rising_edge_flop_clock),
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.enable (clock_enable_when_HIGH), // OPTIONAL
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.load (parallel_load_data_when_HIGH), // OPTIONAL
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.sset (load_data_from_svalue_if_HIGH), // OPTIONAL
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.sclr (set_value_to_0_if_HIGH), // OPTIONAL
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.aset (load_data_from_svalue_if_HIGH), // OPTIONAL
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.aclr (set_value_to_0_if_HIGH) // OPTIONAL
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);
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lpm_ram_dq
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#( 1, // lpm_width
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parameter lpm_widthad = 1;
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parameter lpm_numwords = 1 << lpm_widthad;
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parameter lpm_indata = "REGISTERED";
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parameter lpm_address_control = "REGISTERED";
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parameter lpm_outdata = "REGISTERED";
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parameter lpm_file = "UNUSED";
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) lpm_ram_dq_example (
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.q (data_out[lpm_width-1:0]),
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.data (parallel_data_in[lpm_width-1:0]),
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);
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// NOTE: WORKING
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( q, data, inclock, outclock, we, address );
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input [lpm_width-1:0] data;
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input [lpm_widthad-1:0] address;
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input inclock, outclock, we;
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output [lpm_width-1:0] q;
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lpm_ram_dp
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#( 1, // lpm_width
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parameter lpm_widthad = 1;
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parameter lpm_numwords = 1<< lpm_widthad;
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parameter lpm_indata = "REGISTERED";
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parameter lpm_outdata = "REGISTERED";
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parameter lpm_rdaddress_control = "REGISTERED";
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parameter lpm_wraddress_control = "REGISTERED";
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parameter lpm_file = "UNUSED";
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) lpm_ram_dp_example (
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.q (data_out[lpm_width-1:0]),
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.data (parallel_data_in[lpm_width-1:0]),
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);
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( q, data, wraddress, rdaddress, rdclock, wrclock, rdclken, wrclken, rden, wren);
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input [lpm_width-1:0] data;
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input [lpm_widthad-1:0] rdaddress, wraddress;
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input rdclock, wrclock, rdclken, wrclken, rden, wren;
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output [lpm_width-1:0] q;
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lpm_ram_io
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#( 1, // lpm_width
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parameter lpm_widthad = 1;
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parameter lpm_numwords = 1<< lpm_widthad;
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parameter lpm_indata = "REGISTERED";
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parameter lpm_address_control = "REGISTERED";
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parameter lpm_outdata = "REGISTERED";
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parameter lpm_file = "UNUSED";
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) lpm_ram_io_example (
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.q (data_out[lpm_width-1:0]),
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.data (parallel_data_in[lpm_width-1:0]),
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);
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( dio, inclock, outclock, we, memenab, outenab, address );
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input [lpm_widthad-1:0] address;
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input inclock, outclock, we;
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input memenab;
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input outenab;
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inout [lpm_width-1:0] dio;
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lpm_rom
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#( 1, // lpm_width
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parameter lpm_widthad = 1;
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parameter lpm_numwords = 1<< lpm_widthad;
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parameter lpm_address_control = "REGISTERED";
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parameter lpm_outdata = "REGISTERED";
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parameter lpm_file = "rom.hex";
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) lpm_rom_example (
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.q (data_out[lpm_width-1:0]),
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.data (parallel_data_in[lpm_width-1:0]),
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);
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( q, inclock, outclock, memenab, address );
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input [lpm_widthad-1:0] address;
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input inclock, outclock;
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input memenab;
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output [lpm_width-1:0] q;
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lpm_fifo
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#( 1, // lpm_width
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parameter lpm_widthu = 1;
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parameter lpm_numwords = 2;
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parameter lpm_showahead = "OFF";
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) lpm_fifo_example (
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.q (data_out[lpm_width-1:0]),
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.data (parallel_data_in[lpm_width-1:0]),
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);
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(data, clock, wrreq, rdreq, aclr, sclr, q, usedw, full, empty);
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input [lpm_width-1:0] data;
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input clock;
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input wrreq;
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input rdreq;
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input aclr;
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input sclr;
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output [lpm_width-1:0] q;
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output [lpm_widthu-1:0] usedw;
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output full;
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output empty;
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lpm_fifo_dc
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#( 1, // lpm_width
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parameter lpm_widthu = 1;
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parameter lpm_numwords = 2;
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parameter lpm_showahead = "OFF";
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) lpm_fifo_dc_example (
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.q (data_out[lpm_width-1:0]),
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.data (parallel_data_in[lpm_width-1:0]),
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);
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( data, rdclock, wrclock, aclr, rdreq, wrreq, rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q );
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input [lpm_width-1:0] data;
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input rdclock;
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input wrclock;
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input wrreq;
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input rdreq;
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input aclr;
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output rdfull;
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output wrfull;
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output rdempty;
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output wrempty;
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output [lpm_width-1:0] q;
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output [lpm_widthu-1:0] rdusedw;
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output [lpm_widthu-1:0] wrusedw;
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*/
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//------------------------------------------------------------------------
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// LPM Synthesizable Models
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//------------------------------------------------------------------------
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// Version 1.5 (lpm 220) Date 12/17/99
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//
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// Modified LPM_ADD_SUB and LPM_MULT to accomodate LPM_WIDTH = 1.
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// Default values for LPM_WIDTH* are changed back to 1.
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// Added LPM_HINT to LPM_DIVIDE.
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// Rewritten LPM_FIFO_DC to output correctly.
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// Modified LPM_FIFO to output 0s before first read, output correct
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// values after aclr and sclr, and output LPM_NUMWORDS mod
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// exp(2, LPM_WIDTHU) when FIFO is full.
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//
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//------------------------------------------------------------------------
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// Version 1.4.1 (lpm 220) Date 10/29/99
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//
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// Default values for LPM_WIDTH* of LPM_ADD_SUB and LPM_MULT are changed
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// from 1 to 2.
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//
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//------------------------------------------------------------------------
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// Version 1.4 (lpm 220) Date 10/18/99
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//
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// Default values for each optional inputs for ALL modules are added.
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// Some LPM_PVALUE implementations were missing, and now implemented.
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//
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//------------------------------------------------------------------------
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// Version 1.3 (lpm 220) Date 06/23/99
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//
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// Corrected LPM_FIFO and LPM_FIFO_DC cout and empty/full flags.
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// Implemented LPM_COUNTER cin/cout, and LPM_MODULUS is now working.
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//
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//------------------------------------------------------------------------
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// Version 1.2 (lpm 220) Date 06/16/99
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//
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// Added LPM_RAM_DP, LPM_RAM_DQ, LPM_IO, LPM_ROM, LPM_FIFO, LPM_FIFO_DC.
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// Parameters and ports are added/discarded according to the spec.
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//
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//------------------------------------------------------------------------
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// Version 1.1 (lpm 220) Date 02/05/99
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//
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// Added LPM_DIVIDE module.
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//
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//------------------------------------------------------------------------
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// Version 1.0 Date 07/09/97
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//
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//------------------------------------------------------------------------
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// Excluded Functions:
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//
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// LPM_FSM and LPM_TTABLE.
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//
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//------------------------------------------------------------------------
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// Assumptions:
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//
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// 1. LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, and LPM_NUMWORDS,
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// LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE default value is
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// string UNUSED.
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//
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//------------------------------------------------------------------------
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// Verilog Language Issues:
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//
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// Two dimensional ports are not supported. Modules with two dimensional
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// ports are implemented as one dimensional signal of (LPM_SIZE * LPM_WIDTH)
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// bits wide.
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//
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//------------------------------------------------------------------------
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// Synthesis Issues:
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//
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// 1. LPM_COUNTER
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//
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// Currently synthesis tools do not allow mixing of level and edge
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// sensetive signals. To overcome that problem the "data" signal is
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// removed from the clock always block of lpm_counter, however the
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// synthesis result is accurate. For correct simulation add the "data"
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// pin to the sensetivity list as follows:
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//
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// always @(posedge clock or posedge aclr or posedge aset or
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// posedge aload or data)
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//------------------------------------------------------------------------
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module lpm_latch ( q, data, gate, aset, aclr );
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// NOTE: Parameters must be declared in the same order as the Properties
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// are specified in the Cell Specification document.
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parameter lpm_width = 1;
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parameter lpm_avalue = "UNUSED";
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parameter lpm_pvalue = "UNUSED";
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parameter lpm_type = "lpm_latch";
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parameter lpm_hint = "UNUSED";
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parameter lpm_source_version = "lpm 220 version 1.6";
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input [lpm_width-1:0] data;
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input gate, aset, aclr;
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output [lpm_width-1:0] q;
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reg [lpm_width-1:0] q;
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tri0 aset;
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tri0 aclr;
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buf (i_aset, aset);
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buf (i_aclr, aclr);
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//---------------------------------------------------------------//
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// function integer str_to_int;
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//---------------------------------------------------------------//
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function integer str_to_int;
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input [8*16:1] s;
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reg [8*16:1] reg_s;
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reg [8:1] digit;
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reg [8:1] tmp;
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integer m , ivalue;
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begin
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ivalue = 0;
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reg_s = s;
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for (m=1; m<=16; m= m+1)
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begin
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tmp = reg_s[128:121];
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digit = tmp & 8'b00001111;
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reg_s = reg_s << 8;
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ivalue = ivalue * 10 + digit;
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end
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str_to_int = ivalue;
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end
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endfunction
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//---------------------------------------------------------------//
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initial
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begin
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if (lpm_pvalue != "UNUSED")
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q = str_to_int(lpm_pvalue);
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end
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always @(data or gate or i_aclr or i_aset)
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begin
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if (i_aclr)
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q = 'b0;
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else if (i_aset)
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begin
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if (lpm_avalue == "UNUSED")
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q = {lpm_width{1'b1}};
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else
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q = str_to_int(lpm_avalue);
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end
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else if (gate)
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q = data;
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end
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// Check for previous Parameter declaration order
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initial if ((lpm_width === "lpm_latch") || (lpm_type !== "lpm_latch"))
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begin
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$display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
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$finish;
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end
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endmodule // lpm_latch
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//------------------------------------------------------------------------
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module lpm_ff ( q, data, clock, enable, aclr, aset,
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sclr, sset, aload, sload );
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// NOTE: Parameters must be declared in the same order as the Properties
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// are specified in the Cell Specification document.
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parameter lpm_width = 1;
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parameter lpm_avalue = "UNUSED";
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parameter lpm_svalue = "UNUSED";
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parameter lpm_pvalue = "UNUSED";
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parameter lpm_fftype = "DFF";
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parameter lpm_type = "lpm_ff";
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parameter lpm_hint = "UNUSED";
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parameter lpm_source_version = "lpm 220 version 1.6";
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input [lpm_width-1:0] data;
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input clock, enable;
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input aclr, aset;
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input sclr, sset;
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input aload, sload ;
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output [lpm_width-1:0] q;
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reg [lpm_width-1:0] tmp_q;
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integer i;
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tri1 enable;
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tri0 sload;
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tri0 sclr;
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tri0 sset;
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tri0 aload;
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tri0 aclr;
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tri0 aset;
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buf (i_enable, enable);
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buf (i_sload, sload);
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buf (i_sclr, sclr);
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buf (i_sset, sset);
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buf (i_aload, aload);
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buf (i_aclr, aclr);
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buf (i_aset, aset);
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//---------------------------------------------------------------//
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// function integer str_to_int;
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//---------------------------------------------------------------//
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function integer str_to_int;
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input [8*16:1] s;
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reg [8*16:1] reg_s;
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reg [8:1] digit;
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reg [8:1] tmp;
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integer m , ivalue;
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begin
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ivalue = 0;
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reg_s = s;
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for (m=1; m<=16; m= m+1)
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begin
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tmp = reg_s[128:121];
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digit = tmp & 8'b00001111;
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reg_s = reg_s << 8;
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ivalue = ivalue * 10 + digit;
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end
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str_to_int = ivalue;
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end
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endfunction
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//---------------------------------------------------------------//
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initial
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begin
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if (lpm_pvalue != "UNUSED")
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tmp_q = str_to_int(lpm_pvalue);
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end
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always @(posedge clock or posedge i_aclr or posedge i_aset or
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posedge i_aload)
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begin :asyn_block // Asynchronous process
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if (i_aclr)
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begin
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tmp_q = 0;
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end
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else if (i_aset)
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begin
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if (lpm_avalue == "UNUSED")
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tmp_q = {lpm_width{1'b1}};
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else
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tmp_q = str_to_int(lpm_avalue);
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end
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else if (i_aload)
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begin
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tmp_q = data;
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end
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else
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begin :syn_block // Synchronous process
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if (i_enable)
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begin
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if (i_sclr)
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begin
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tmp_q = 0;
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end
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else if (i_sset)
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begin
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if (lpm_svalue == "UNUSED")
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tmp_q = {lpm_width{1'b1}};
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else
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tmp_q = str_to_int(lpm_svalue);
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end
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else if (i_sload) // Load data
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begin
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tmp_q = data;
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end
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else
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begin
|
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if (lpm_fftype == "TFF") // toggle
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begin
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for (i = 0; i < lpm_width; i=i+1)
|
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begin
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if (data[i] == 1'b1)
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tmp_q[i] = ~tmp_q[i];
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end
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end
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else
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if (lpm_fftype == "DFF") // load data
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tmp_q = data;
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end
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end
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end
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end
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assign q = tmp_q;
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|
|
// Check for previous Parameter declaration order
|
|
initial if ((lpm_width === "lpm_ff") || (lpm_type !== "lpm_ff"))
|
|
begin
|
|
$display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
|
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$finish;
|
|
end
|
|
endmodule // lpm_ff
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|
//------------------------------------------------------------------------
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module lpm_shiftreg ( q, shiftout, data, clock, enable, aclr, aset,
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sclr, sset, shiftin, load );
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// NOTE: Parameters must be declared in the same order as the Properties
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// are specified in the Cell Specification document.
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parameter lpm_width = 1;
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parameter lpm_avalue = "UNUSED";
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parameter lpm_svalue = "UNUSED";
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parameter lpm_pvalue = "UNUSED";
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parameter lpm_direction = "LEFT";
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parameter lpm_type = "lpm_shiftreg";
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parameter lpm_hint = "UNUSED";
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parameter lpm_source_version = "lpm 220 version 1.6";
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input [lpm_width-1:0] data;
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input clock, enable;
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input aclr, aset;
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input sclr, sset;
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input shiftin, load;
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output [lpm_width-1:0] q;
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output shiftout;
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reg [lpm_width-1:0] tmp_q;
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reg abit;
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integer i;
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wire tmp_shiftout;
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tri1 enable;
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tri1 shiftin;
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tri0 load;
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tri0 sclr;
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tri0 sset;
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tri0 aclr;
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tri0 aset;
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buf (i_enable, enable);
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buf (i_shiftin, shiftin);
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buf (i_load, load);
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buf (i_sclr, sclr);
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buf (i_sset, sset);
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buf (i_aclr, aclr);
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buf (i_aset, aset);
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//---------------------------------------------------------------//
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// function integer str_to_int;
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//---------------------------------------------------------------//
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function integer str_to_int;
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input [8*16:1] s;
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reg [8*16:1] reg_s;
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reg [8:1] digit;
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reg [8:1] tmp;
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integer m , ivalue;
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begin
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ivalue = 0;
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reg_s = s;
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for (m=1; m<=16; m= m+1)
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begin
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tmp = reg_s[128:121];
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digit = tmp & 8'b00001111;
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reg_s = reg_s << 8;
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ivalue = ivalue * 10 + digit;
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end
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str_to_int = ivalue;
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end
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endfunction
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//---------------------------------------------------------------//
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initial
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begin
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if (lpm_pvalue != "UNUSED")
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tmp_q = str_to_int(lpm_pvalue);
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end
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always @(posedge clock or posedge i_aclr or posedge i_aset)
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begin :asyn_block // Asynchronous process
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if (i_aclr)
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begin
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tmp_q = 0;
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end
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else if (i_aset)
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begin
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if (lpm_avalue === "UNUSED")
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tmp_q = {lpm_width{1'b1}};
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else
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tmp_q = str_to_int(lpm_avalue);
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end
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else
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begin :syn_block // Synchronous process
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if (i_enable)
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begin
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if (i_sclr)
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begin
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tmp_q = 0;
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end
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else if (i_sset)
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begin
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if (lpm_svalue === "UNUSED")
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tmp_q = {lpm_width{1'b1}};
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else
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tmp_q = str_to_int(lpm_svalue);
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end
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else if (i_load)
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begin
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tmp_q = data;
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end
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else if (!i_load)
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begin
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if (lpm_direction === "LEFT")
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begin
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{abit,tmp_q} = {tmp_q,i_shiftin};
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end
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else if (lpm_direction === "RIGHT")
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begin
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{tmp_q,abit} = {i_shiftin,tmp_q};
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end
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end
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end
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end
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end
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assign tmp_shiftout = (lpm_direction === "LEFT") ? tmp_q[lpm_width-1]
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: tmp_q[0];
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assign q = tmp_q;
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assign shiftout = tmp_shiftout;
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// Check for previous Parameter declaration order
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initial if ((lpm_width === "lpm_shiftreg") || (lpm_type !== "lpm_shiftreg"))
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begin
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$display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
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$finish;
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end
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endmodule // lpm_shiftreg
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//------------------------------------------------------------------------
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module lpm_ram_dq ( q, data, inclock, outclock, we, address );
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// NOTE: Parameters must be declared in the same order as the Properties
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// are specified in the Cell Specification document.
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parameter lpm_width = 1;
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parameter lpm_widthad = 1;
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parameter lpm_numwords = 1 << lpm_widthad;
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parameter lpm_indata = "REGISTERED";
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parameter lpm_address_control = "REGISTERED";
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parameter lpm_outdata = "REGISTERED";
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parameter lpm_file = "UNUSED";
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parameter lpm_type = "lpm_ram_dq";
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parameter lpm_hint = "UNUSED";
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parameter lpm_source_version = "lpm 220 version 1.6";
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input [lpm_width-1:0] data;
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input [lpm_widthad-1:0] address;
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input inclock, outclock, we;
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output [lpm_width-1:0] q;
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// internal reg
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reg [lpm_width-1:0] mem_data [lpm_numwords-1:0];
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reg [lpm_width-1:0] tmp_q;
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reg [lpm_width-1:0] pdata;
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reg [lpm_width-1:0] in_data;
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reg [lpm_widthad-1:0] paddress;
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reg pwe;
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reg [lpm_width-1:0] ZEROS, UNKNOWN;
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reg [8*256:1] ram_initf;
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integer i;
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tri0 inclock;
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tri0 outclock;
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buf (i_inclock, inclock);
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buf (i_outclock, outclock);
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//---------------------------------------------------------------//
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function ValidAddress;
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input [lpm_widthad-1:0] paddress;
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begin
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ValidAddress = 1'b0;
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if (^paddress ==='bx)
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$display("%d:Error! Invalid address.\n", $time);
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else if (paddress >= lpm_numwords)
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$display("%d:Error! Address out of bound on RAM.\n", $time);
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else
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ValidAddress = 1'b1;
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end
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endfunction
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//---------------------------------------------------------------//
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initial
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begin
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// Initialize the internal data register.
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pdata = 0;
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paddress = 0;
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pwe = 0;
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tmp_q = 0;
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if (lpm_width <= 0)
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$display("Error! lpm_width parameter must be greater than 0.");
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if (lpm_widthad <= 0)
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$display("Error! lpm_widthad parameter must be greater than 0.");
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// check for number of words out of bound
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if ((lpm_numwords > (1 << lpm_widthad))
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||(lpm_numwords <= (1 << (lpm_widthad-1))))
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begin
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$display("Error! lpm_numwords must equal to the ceiling of log2(lpm_widthad).");
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end
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if ((lpm_indata !== "REGISTERED") && (lpm_indata !== "UNREGISTERED"))
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begin
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$display("Error! lpm_indata must be REGISTERED (the default) or UNREGISTERED.");
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end
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if ((lpm_address_control !== "REGISTERED") && (lpm_address_control !== "UNREGISTERED"))
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begin
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$display("Error! lpm_address_control must be REGISTERED (the default) or UNREGISTERED.");
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end
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if ((lpm_outdata !== "REGISTERED") && (lpm_outdata !== "UNREGISTERED"))
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begin
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$display("Error! lpm_outdata must be REGISTERED (the default) or UNREGISTERED.");
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end
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// check if lpm_indata or lpm_address_control is set to registered
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// inclock must be used.
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if (((lpm_indata === "REGISTERED") || (lpm_address_control === "REGISTERED")) && (inclock === 1'bz))
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begin
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$display("Error! inclock = 1'bz. Inclock pin must be used.\n");
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end
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// check if lpm_outdata, outclock must be used
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if ((lpm_outdata === "REGISTERED") && (outclock === 1'bz))
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begin
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$display("Error! lpm_outdata = REGISTERED, outclock = 1'bz . Outclock pin must be used.\n");
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|
end
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|
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for (i=0; i < lpm_width; i=i+1)
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|
begin
|
|
ZEROS[i] = 1'b0;
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UNKNOWN[i] = 1'bX;
|
|
end
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|
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for (i = 0; i < lpm_numwords; i=i+1)
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|
mem_data[i] = ZEROS;
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|
|
// load data to the RAM
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|
if (lpm_file != "UNUSED")
|
|
begin
|
|
$convert_hex2ver(lpm_file, lpm_width, ram_initf);
|
|
$readmemh(ram_initf, mem_data);
|
|
end
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|
|
end
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always @(posedge i_inclock)
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begin
|
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if ((lpm_indata === "REGISTERED") && (lpm_address_control === "REGISTERED"))
|
|
begin
|
|
paddress <= address;
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pdata <= data;
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pwe <= we;
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end
|
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else
|
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begin
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if ((lpm_indata === "REGISTERED") && (lpm_address_control === "UNREGISTERED"))
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pdata <= data;
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if ((lpm_indata === "UNREGISTERED") && (lpm_address_control === "REGISTERED"))
|
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begin
|
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paddress <= address;
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pwe <= we;
|
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end
|
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end
|
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end
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|
always @(data)
|
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begin
|
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if (lpm_indata === "UNREGISTERED")
|
|
pdata <= data;
|
|
end
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always @(address)
|
|
begin
|
|
if (lpm_address_control === "UNREGISTERED")
|
|
paddress <= address;
|
|
end
|
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|
always @(we)
|
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begin
|
|
if (lpm_address_control === "UNREGISTERED")
|
|
pwe <= we;
|
|
end
|
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|
always @(pdata or paddress or pwe)
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begin :unregistered_inclock
|
|
if (ValidAddress(paddress))
|
|
begin
|
|
if ((lpm_indata === "UNREGISTERED" && lpm_address_control === "UNREGISTERED") || (lpm_address_control === "UNREGISTERED"))
|
|
begin
|
|
if (pwe)
|
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mem_data[paddress] <= pdata;
|
|
end
|
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|
|
end
|
|
else
|
|
begin
|
|
if (lpm_outdata === "UNREGISTERED")
|
|
tmp_q <= UNKNOWN;
|
|
end
|
|
end
|
|
|
|
always @(posedge i_outclock)
|
|
begin
|
|
if (lpm_outdata === "REGISTERED")
|
|
begin
|
|
if (ValidAddress(paddress))
|
|
tmp_q <= mem_data[paddress];
|
|
else
|
|
tmp_q <= UNKNOWN;
|
|
end
|
|
end
|
|
|
|
always @(negedge i_inclock)
|
|
begin
|
|
if (lpm_address_control === "REGISTERED")
|
|
begin
|
|
if (pwe)
|
|
mem_data[paddress] <= pdata;
|
|
end
|
|
end
|
|
|
|
assign q = ( lpm_outdata === "UNREGISTERED" ) ? mem_data[paddress] : tmp_q;
|
|
|
|
// Check for previous Parameter declaration order
|
|
initial if ((lpm_width === "lpm_ram_dq") || (lpm_type !== "lpm_ram_dq"))
|
|
begin
|
|
$display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
|
|
$finish;
|
|
end
|
|
endmodule // lpm_ram_dq
|
|
|
|
//------------------------------------------------------------------------
|
|
|
|
module lpm_ram_dp ( q, data, wraddress, rdaddress, rdclock, wrclock, rdclken, wrclken, rden, wren);
|
|
|
|
// NOTE: Parameters must be declared in the same order as the Properties
|
|
// are specified in the Cell Specification document.
|
|
parameter lpm_width = 1;
|
|
parameter lpm_widthad = 1;
|
|
parameter lpm_numwords = 1<< lpm_widthad;
|
|
parameter lpm_indata = "REGISTERED";
|
|
parameter lpm_outdata = "REGISTERED";
|
|
parameter lpm_rdaddress_control = "REGISTERED";
|
|
parameter lpm_wraddress_control = "REGISTERED";
|
|
parameter lpm_file = "UNUSED";
|
|
parameter lpm_type = "lpm_ram_dp";
|
|
parameter lpm_hint = "UNUSED";
|
|
parameter lpm_source_version = "lpm 220 version 1.6";
|
|
|
|
input [lpm_width-1:0] data;
|
|
input [lpm_widthad-1:0] rdaddress, wraddress;
|
|
input rdclock, wrclock, rdclken, wrclken, rden, wren;
|
|
output [lpm_width-1:0] q;
|
|
|
|
|
|
// internal reg
|
|
reg [lpm_width-1:0] mem_data [lpm_numwords-1:0];
|
|
reg [lpm_width-1:0] tmp_q;
|
|
reg [lpm_width-1:0] prev_q;
|
|
reg [lpm_width-1:0] new_data;
|
|
reg [lpm_widthad-1:0] new_raddress;
|
|
reg [lpm_widthad-1:0] new_wraddress;
|
|
reg wren_event, rden_event;
|
|
reg [lpm_width-1:0] ZEROS, UNKNOWN;
|
|
reg [8*256:1] ram_initf;
|
|
integer i;
|
|
|
|
tri0 rdclock;
|
|
tri1 rdclken;
|
|
tri1 rden;
|
|
tri0 wrclock;
|
|
tri1 wrclken;
|
|
|
|
buf (i_rdclock, rdclock);
|
|
buf (i_rdclken, rdclken);
|
|
buf (i_rden, rden);
|
|
buf (i_wrclock, wrclock);
|
|
buf (i_wrclken, wrclken);
|
|
|
|
|
|
//---------------------------------------------------------------//
|
|
function ValidAddress;
|
|
input [lpm_widthad-1:0] paddress;
|
|
|
|
begin
|
|
ValidAddress = 1'b0;
|
|
if (^paddress ==='bx)
|
|
$display("%d:Error! Invalid address.\n", $time);
|
|
else if (paddress >= lpm_numwords)
|
|
$display("%d:Error! Address out of bound on RAM.\n", $time);
|
|
else
|
|
ValidAddress = 1'b1;
|
|
end
|
|
endfunction
|
|
//---------------------------------------------------------------//
|
|
|
|
initial
|
|
begin
|
|
|
|
// Initialize the internal data register.
|
|
new_data = 0;
|
|
new_raddress = 0;
|
|
new_wraddress = 0;
|
|
wren_event = 0;
|
|
tmp_q = 0;
|
|
|
|
if (lpm_width <= 0)
|
|
$display("Error! lpm_width parameter must be greater than 0.");
|
|
|
|
if (lpm_widthad <= 0)
|
|
$display("Error! lpm_widthad parameter must be greater than 0.");
|
|
// check for number of words out of bound
|
|
if ((lpm_numwords > (1 << lpm_widthad))
|
|
||(lpm_numwords <= (1 << (lpm_widthad-1))))
|
|
begin
|
|
$display("Error! lpm_numwords must equal to the ceiling of log2(lpm_widthad).");
|
|
end
|
|
|
|
if ((lpm_indata !== "REGISTERED") && (lpm_indata !== "UNREGISTERED"))
|
|
begin
|
|
$display("Error! lpm_indata must be REGISTERED (the default) or UNREGISTERED.");
|
|
end
|
|
|
|
if ((lpm_rdaddress_control !== "REGISTERED") && (lpm_rdaddress_control !== "UNREGISTERED"))
|
|
begin
|
|
$display("Error! lpm_rdaddress_control must be REGISTERED (the default) or UNREGISTERED.");
|
|
end
|
|
|
|
if ((lpm_wraddress_control !== "REGISTERED") && (lpm_wraddress_control !== "UNREGISTERED"))
|
|
begin
|
|
$display("Error! lpm_wraddress_control must be REGISTERED (the default) or UNREGISTERED.");
|
|
end
|
|
|
|
if ((lpm_outdata !== "REGISTERED") && (lpm_outdata !== "UNREGISTERED"))
|
|
begin
|
|
$display("Error! lpm_outdata must be REGISTERED (the default) or UNREGISTERED.");
|
|
end
|
|
|
|
// check if lpm_indata or lpm_wraddress_control is set to registered
|
|
// wrclock and wrclken must be used.
|
|
if (((lpm_indata === "REGISTERED") || (lpm_wraddress_control === "REGISTERED")) && ((wrclock === 1'bz) || (wrclken == 1'bz)))
|
|
begin
|
|
$display("Error! wrclock = 1'bz. wrclock and wrclken pins must be used.\n");
|
|
end
|
|
|
|
// check if lpm_rdaddress_control is set to registered
|
|
// rdclock and rdclken must be used.
|
|
if ((lpm_rdaddress_control === "REGISTERED") && ((rdclock === 1'bz) || (rdclken == 1'bz)))
|
|
begin
|
|
$display("Error! rdclock = 1'bz. rdclock and rdclken pins must be used.\n");
|
|
end
|
|
|
|
// check if lpm_outdata, rdclock must be used
|
|
if ((lpm_outdata === "REGISTERED") && (rdclock === 1'bz))
|
|
begin
|
|
$display("Error! lpm_outdata = REGISTERED, rdclock = 1'bz . rdclock pnd rdclken pins must be used.\n");
|
|
end
|
|
|
|
for (i=0; i < lpm_width; i=i+1)
|
|
begin
|
|
ZEROS[i] = 1'b0;
|
|
UNKNOWN[i] = 1'bX;
|
|
end
|
|
|
|
for (i = 0; i < lpm_numwords; i=i+1)
|
|
mem_data[i] = ZEROS;
|
|
|
|
// load data to the RAM
|
|
if (lpm_file != "UNUSED")
|
|
begin
|
|
$convert_hex2ver(lpm_file, lpm_width, ram_initf);
|
|
$readmemh(ram_initf, mem_data);
|
|
end
|
|
end
|
|
|
|
|
|
always @(posedge i_wrclock)
|
|
begin
|
|
if (i_wrclken)
|
|
begin
|
|
if ((lpm_indata === "REGISTERED") && (lpm_wraddress_control === "REGISTERED"))
|
|
begin
|
|
new_wraddress <= wraddress;
|
|
new_data <= data;
|
|
wren_event <= wren;
|
|
end
|
|
else
|
|
begin
|
|
if ((lpm_indata === "REGISTERED") && (lpm_wraddress_control === "UNREGISTERED"))
|
|
new_data <= data;
|
|
|
|
if ((lpm_indata === "UNREGISTERED") && (lpm_wraddress_control === "REGISTERED"))
|
|
begin
|
|
new_wraddress <= wraddress;
|
|
wren_event <= wren;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
|
|
always @(data)
|
|
begin
|
|
if (lpm_indata === "UNREGISTERED")
|
|
new_data <= data;
|
|
end
|
|
|
|
always @(wraddress)
|
|
begin
|
|
if (lpm_wraddress_control === "UNREGISTERED")
|
|
new_wraddress <= wraddress;
|
|
end
|
|
|
|
always @(rdaddress)
|
|
begin
|
|
if (lpm_rdaddress_control === "UNREGISTERED")
|
|
new_raddress <= rdaddress;
|
|
end
|
|
|
|
always @(wren)
|
|
begin
|
|
if (lpm_wraddress_control === "UNREGISTERED")
|
|
wren_event <= wren;
|
|
end
|
|
|
|
always @(i_rden)
|
|
begin
|
|
if (lpm_rdaddress_control === "UNREGISTERED")
|
|
rden_event <= i_rden;
|
|
end
|
|
|
|
always @(new_data or new_wraddress or wren_event)
|
|
begin
|
|
if (ValidAddress(new_wraddress))
|
|
begin
|
|
if ((wren_event) && (i_wrclken))
|
|
mem_data[new_wraddress] <= new_data;
|
|
end
|
|
else
|
|
begin
|
|
if (lpm_outdata === "UNREGISTERED")
|
|
tmp_q <= UNKNOWN;
|
|
end
|
|
end
|
|
|
|
always @(posedge i_rdclock)
|
|
begin
|
|
if (lpm_rdaddress_control == "REGISTERED")
|
|
if (i_rdclken)
|
|
begin
|
|
new_raddress <= rdaddress;
|
|
rden_event <= i_rden;
|
|
end
|
|
if (lpm_outdata === "REGISTERED")
|
|
begin
|
|
if ((i_rdclken) && (rden_event))
|
|
begin
|
|
if (ValidAddress(new_raddress))
|
|
begin
|
|
tmp_q <= mem_data[new_raddress];
|
|
end
|
|
else
|
|
tmp_q <= UNKNOWN;
|
|
end
|
|
end
|
|
end
|
|
|
|
//assign q = ( lpm_outdata === "UNREGISTERED" ) ? mem_data[new_raddress] : tmp_q;
|
|
|
|
always @(mem_data[new_raddress] or tmp_q or i_rden)
|
|
begin
|
|
if (i_rden || lpm_outdata === "REGISTERED")
|
|
prev_q <= ( lpm_outdata === "UNREGISTERED" ) ? mem_data[new_raddress] : tmp_q;
|
|
end
|
|
|
|
assign q = prev_q;
|
|
|
|
// Check for previous Parameter declaration order
|
|
initial if ((lpm_width === "lpm_ram_dp") || (lpm_type !== "lpm_ram_dp"))
|
|
begin
|
|
$display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
|
|
$finish;
|
|
end
|
|
endmodule // lpm_ram_dp
|
|
|
|
//------------------------------------------------------------------------
|
|
|
|
module lpm_ram_io ( dio, inclock, outclock, we, memenab, outenab, address );
|
|
|
|
// NOTE: Parameters must be declared in the same order as the Properties
|
|
// are specified in the Cell Specification document.
|
|
parameter lpm_width = 1;
|
|
parameter lpm_widthad = 1;
|
|
parameter lpm_numwords = 1<< lpm_widthad;
|
|
parameter lpm_indata = "REGISTERED";
|
|
parameter lpm_address_control = "REGISTERED";
|
|
parameter lpm_outdata = "REGISTERED";
|
|
parameter lpm_file = "UNUSED";
|
|
parameter lpm_type = "lpm_ram_io";
|
|
parameter lpm_hint = "UNUSED";
|
|
parameter lpm_source_version = "lpm 220 version 1.6";
|
|
|
|
input [lpm_widthad-1:0] address;
|
|
input inclock, outclock, we;
|
|
input memenab;
|
|
input outenab;
|
|
inout [lpm_width-1:0] dio;
|
|
|
|
|
|
// inernal reg
|
|
reg [lpm_width-1:0] mem_data [lpm_numwords-1:0];
|
|
reg [lpm_width-1:0] tmp_io;
|
|
reg [lpm_width-1:0] tmp_q;
|
|
reg [lpm_width-1:0] pdio;
|
|
reg [lpm_widthad-1:0] paddress;
|
|
reg pwe;
|
|
reg [lpm_width-1:0] ZEROS, UNKNOWN, HiZ;
|
|
reg [8*256:1] ram_initf;
|
|
integer i;
|
|
|
|
tri0 inclock;
|
|
tri0 outclock;
|
|
|
|
buf (i_inclock, inclock);
|
|
buf (i_outclock, outclock);
|
|
|
|
|
|
//---------------------------------------------------------------//
|
|
function ValidAddress;
|
|
input [lpm_widthad-1:0] paddress;
|
|
|
|
begin
|
|
ValidAddress = 1'b0;
|
|
if (^paddress ==='bx)
|
|
$display("%d:Error: Invalid address.", $time);
|
|
else if (paddress >= lpm_numwords)
|
|
$display("%d:Error: Address out of bound on RAM.", $time);
|
|
else
|
|
ValidAddress = 1'b1;
|
|
end
|
|
endfunction
|
|
//---------------------------------------------------------------//
|
|
|
|
initial
|
|
begin
|
|
|
|
if (lpm_width <= 0)
|
|
$display("Error! lpm_width parameter must be greater than 0.");
|
|
|
|
if (lpm_widthad <= 0)
|
|
$display("Error! lpm_widthad parameter must be greater than 0.");
|
|
|
|
// check for number of words out of bound
|
|
if ((lpm_numwords > (1 << lpm_widthad))
|
|
||(lpm_numwords <= (1 << (lpm_widthad-1))))
|
|
begin
|
|
$display("Error! lpm_numwords must equal to the ceiling of log2(lpm_widthad).");
|
|
end
|
|
|
|
if ((lpm_indata !== "REGISTERED") && (lpm_indata !== "UNREGISTERED"))
|
|
begin
|
|
$display("Error! lpm_indata must be REGISTERED (the default) or UNREGISTERED.");
|
|
end
|
|
|
|
if ((lpm_address_control !== "REGISTERED") && (lpm_address_control !== "UNREGISTERED"))
|
|
begin
|
|
$display("Error! lpm_address_control must be REGISTERED (the default) or UNREGISTERED.");
|
|
end
|
|
|
|
if ((lpm_outdata !== "REGISTERED") && (lpm_outdata !== "UNREGISTERED"))
|
|
begin
|
|
$display("Error! lpm_outdata must be REGISTERED (the default) or UNREGISTERED.");
|
|
end
|
|
|
|
|
|
// check if lpm_indata or lpm_address_control is set to registered
|
|
// inclock must be used.
|
|
if (((lpm_indata === "REGISTERED") || (lpm_address_control === "REGISTERED")) && (inclock === 1'bz))
|
|
begin
|
|
$display("Error! inclock = 1'bz. Inclock pin must be used.\n");
|
|
end
|
|
|
|
// check if lpm_outdata, outclock must be used
|
|
if ((lpm_outdata === "REGISTERED") && (outclock === 1'bz))
|
|
begin
|
|
$display("Error! lpm_outdata is REGISTERED, outclock = 1'bz. Outclock pin must be used.\n");
|
|
end
|
|
|
|
for (i=0; i < lpm_width; i=i+1)
|
|
begin
|
|
ZEROS[i] = 1'b0;
|
|
UNKNOWN[i] = 1'bX;
|
|
HiZ[i] = 1'bZ;
|
|
end
|
|
|
|
for (i = 0; i < lpm_numwords; i=i+1)
|
|
mem_data[i] = ZEROS;
|
|
|
|
// Initialize input/output
|
|
pdio = 0;
|
|
paddress = 0;
|
|
tmp_io = 0;
|
|
tmp_q = 0;
|
|
|
|
// load data to the RAM
|
|
if (lpm_file != "UNUSED")
|
|
begin
|
|
$convert_hex2ver(lpm_file, lpm_width, ram_initf);
|
|
$readmemh(ram_initf, mem_data);
|
|
end
|
|
end
|
|
|
|
|
|
always @(dio)
|
|
begin
|
|
if (lpm_indata === "UNREGISTERED")
|
|
pdio <= dio;
|
|
end
|
|
|
|
always @(address)
|
|
begin
|
|
if (lpm_address_control === "UNREGISTERED")
|
|
paddress <= address;
|
|
end
|
|
|
|
|
|
always @(we)
|
|
begin
|
|
if (lpm_address_control === "UNREGISTERED")
|
|
pwe <= we;
|
|
end
|
|
|
|
always @(posedge i_inclock)
|
|
begin
|
|
if (lpm_indata === "REGISTERED")
|
|
pdio <= dio;
|
|
|
|
if (lpm_address_control === "REGISTERED")
|
|
begin
|
|
paddress <= address;
|
|
pwe <= we;
|
|
end
|
|
end
|
|
|
|
always @(pdio or paddress or pwe or memenab)
|
|
begin :block_a
|
|
if (ValidAddress(paddress))
|
|
begin
|
|
if ((lpm_indata === "UNREGISTERED" && lpm_address_control === "UNREGISTERED") || (lpm_address_control === "UNREGISTERED"))
|
|
begin
|
|
if (pwe && memenab)
|
|
mem_data[paddress] <= pdio;
|
|
end
|
|
|
|
if (lpm_outdata === "UNREGISTERED")
|
|
begin
|
|
tmp_q <= mem_data[paddress];
|
|
tmp_q <= mem_data[paddress];
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if (lpm_outdata === "UNREGISTERED")
|
|
tmp_q <= UNKNOWN;
|
|
end
|
|
end
|
|
|
|
always @(negedge i_inclock)
|
|
begin
|
|
if (lpm_address_control === "REGISTERED")
|
|
begin
|
|
if (pwe && memenab)
|
|
mem_data[paddress] <= pdio;
|
|
end
|
|
end
|
|
|
|
always @(posedge i_outclock)
|
|
begin
|
|
if (lpm_outdata === "REGISTERED")
|
|
begin
|
|
tmp_q <= mem_data[paddress];
|
|
end
|
|
end
|
|
|
|
always @(memenab or outenab or tmp_q)
|
|
begin
|
|
if (memenab && outenab)
|
|
tmp_io <= tmp_q;
|
|
else if (!memenab || (memenab && !outenab))
|
|
tmp_io <= HiZ;
|
|
end
|
|
|
|
assign dio = tmp_io;
|
|
|
|
// Check for previous Parameter declaration order
|
|
initial if ((lpm_width === "lpm_ram_io") || (lpm_type !== "lpm_ram_io"))
|
|
begin
|
|
$display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
|
|
$finish;
|
|
end
|
|
endmodule // lpm_ram_io
|
|
|
|
//------------------------------------------------------------------------
|
|
|
|
module lpm_rom ( q, inclock, outclock, memenab, address );
|
|
|
|
// NOTE: Parameters must be declared in the same order as the Properties
|
|
// are specified in the Cell Specification document.
|
|
parameter lpm_width = 1;
|
|
parameter lpm_widthad = 1;
|
|
parameter lpm_numwords = 1<< lpm_widthad;
|
|
parameter lpm_address_control = "REGISTERED";
|
|
parameter lpm_outdata = "REGISTERED";
|
|
parameter lpm_file = "rom.hex";
|
|
parameter lpm_type = "lpm_rom";
|
|
parameter lpm_hint = "UNUSED";
|
|
parameter lpm_source_version = "lpm 220 version 1.6";
|
|
|
|
input [lpm_widthad-1:0] address;
|
|
input inclock, outclock;
|
|
input memenab;
|
|
output [lpm_width-1:0] q;
|
|
|
|
// inernal reg
|
|
reg [lpm_width-1:0] mem_data [lpm_numwords-1:0];
|
|
reg [lpm_widthad-1:0] paddress;
|
|
reg [lpm_width-1:0] tmp_q;
|
|
reg [lpm_width-1:0] tmp_q_reg;
|
|
reg [lpm_width-1:0] ZEROS, UNKNOWN, HiZ;
|
|
reg [8*256:1] rom_initf;
|
|
integer i;
|
|
|
|
tri0 inclock;
|
|
tri0 outclock;
|
|
tri1 memenab;
|
|
|
|
buf (i_inclock, inclock);
|
|
buf (i_outclock, outclock);
|
|
buf (i_memenab, memenab);
|
|
|
|
|
|
//---------------------------------------------------------------//
|
|
function ValidAddress;
|
|
input [lpm_widthad-1:0] address;
|
|
begin
|
|
ValidAddress = 1'b0;
|
|
if (^address =='bx)
|
|
$display("%d:Error: Invalid address.", $time);
|
|
else if (address >= lpm_numwords)
|
|
$display("%d:Error: Address out of bound on ROM.", $time);
|
|
else
|
|
ValidAddress = 1'b1;
|
|
end
|
|
endfunction
|
|
//---------------------------------------------------------------//
|
|
|
|
initial
|
|
begin
|
|
// Initialize output
|
|
tmp_q = 0;
|
|
tmp_q_reg = 0;
|
|
paddress = 0;
|
|
|
|
if (lpm_file === "")
|
|
$display("Error! rom module must have data file for initialization\n.");
|
|
|
|
if (lpm_width <= 0)
|
|
$display("Error! lpm_width parameter must be greater than 0.");
|
|
|
|
if (lpm_widthad <= 0)
|
|
$display("Error! lpm_widthad parameter must be greater than 0.");
|
|
|
|
|
|
// check for number of words out of bound
|
|
if ((lpm_numwords > (1 << lpm_widthad))
|
|
||(lpm_numwords <= (1 << (lpm_widthad-1))))
|
|
begin
|
|
$display("Error! lpm_numwords must equal to the ceiling of log2(lpm_widthad).");
|
|
end
|
|
|
|
if ((lpm_address_control !== "REGISTERED") && (lpm_address_control !== "UNREGISTERED"))
|
|
begin
|
|
$display("Error! lpm_address_control must be REGISTERED (the default) or UNREGISTERED.");
|
|
end
|
|
|
|
if ((lpm_outdata !== "REGISTERED") && (lpm_outdata !== "UNREGISTERED"))
|
|
begin
|
|
$display("Error! lpm_outdata must be REGISTERED (the default) or UNREGISTERED.");
|
|
end
|
|
|
|
// check if lpm_address_control is set to registered
|
|
// inclock must be used.
|
|
if ((lpm_address_control === "REGISTERED") && (inclock === 1'bz))
|
|
begin
|
|
$display("Error! inclock = 1'bz. Inclock pin must be used.\n");
|
|
end
|
|
|
|
// check if lpm_outdata, outclock must be used
|
|
if ((lpm_outdata === "REGISTERED") && (outclock === 1'bz))
|
|
begin
|
|
$display("Error! lpm_outdata is REGISTERED, outclock = 1'bz. Outclock must be used.\n");
|
|
end
|
|
|
|
for (i=0; i < lpm_width; i=i+1)
|
|
begin
|
|
ZEROS[i] = 1'b0;
|
|
UNKNOWN[i] = 1'bX;
|
|
HiZ[i] = 1'bZ;
|
|
end
|
|
|
|
for (i = 0; i < lpm_numwords; i=i+1)
|
|
mem_data[i] = ZEROS;
|
|
|
|
// load data to the ROM
|
|
if (lpm_file != "")
|
|
begin
|
|
$convert_hex2ver(lpm_file, lpm_width, rom_initf);
|
|
$readmemh(rom_initf, mem_data);
|
|
end
|
|
end
|
|
|
|
always @(posedge i_inclock)
|
|
begin
|
|
if (lpm_address_control === "REGISTERED")
|
|
paddress <= address;
|
|
end
|
|
|
|
always @(address)
|
|
begin
|
|
if (lpm_address_control === "UNREGISTERED")
|
|
paddress <= address;
|
|
end
|
|
|
|
|
|
always @(paddress)
|
|
begin
|
|
if (ValidAddress(paddress))
|
|
begin
|
|
if (lpm_outdata === "UNREGISTERED")
|
|
tmp_q_reg <= mem_data[paddress];
|
|
end
|
|
else
|
|
begin
|
|
if (lpm_outdata === "UNREGISTERED")
|
|
tmp_q_reg <= UNKNOWN;
|
|
end
|
|
end
|
|
|
|
always @(posedge i_outclock)
|
|
begin
|
|
if (lpm_outdata === "REGISTERED")
|
|
begin
|
|
if (ValidAddress(paddress))
|
|
tmp_q_reg <= mem_data[paddress];
|
|
else
|
|
tmp_q_reg <= UNKNOWN;
|
|
end
|
|
end
|
|
|
|
|
|
always @(i_memenab or tmp_q_reg)
|
|
begin
|
|
if (i_memenab)
|
|
tmp_q <= tmp_q_reg;
|
|
else if (!i_memenab)
|
|
tmp_q <= HiZ;
|
|
end
|
|
|
|
assign q = tmp_q;
|
|
|
|
// Check for previous Parameter declaration order
|
|
initial if ((lpm_width === "lpm_rom") || (lpm_type !== "lpm_rom"))
|
|
begin
|
|
$display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
|
|
$finish;
|
|
end
|
|
endmodule // lpm_rom
|
|
|
|
//------------------------------------------------------------------------
|
|
|
|
module lpm_fifo (data, clock, wrreq, rdreq, aclr, sclr, q, usedw, full, empty);
|
|
|
|
// NOTE: Parameters must be declared in the same order as the Properties
|
|
// are specified in the Cell Specification document.
|
|
parameter lpm_width = 1;
|
|
parameter lpm_widthu = 1;
|
|
parameter lpm_numwords = 2;
|
|
parameter lpm_showahead = "OFF";
|
|
parameter lpm_type = "lpm_fifo";
|
|
parameter lpm_hint = "UNUSED";
|
|
parameter lpm_source_version = "lpm 220 version 1.6";
|
|
|
|
input [lpm_width-1:0] data;
|
|
input clock;
|
|
input wrreq;
|
|
input rdreq;
|
|
input aclr;
|
|
input sclr;
|
|
output [lpm_width-1:0] q;
|
|
output [lpm_widthu-1:0] usedw;
|
|
output full;
|
|
output empty;
|
|
|
|
|
|
// internal reg
|
|
reg [lpm_width-1:0] mem_data [lpm_numwords-1:0];
|
|
reg [lpm_width-1:0] tmp_q;
|
|
reg [lpm_width-1:0] ZEROS;
|
|
reg [lpm_widthu+1:0] count_id;
|
|
reg [lpm_widthu-1:0] write_id;
|
|
reg [lpm_widthu-1:0] read_id;
|
|
reg empty_flag;
|
|
reg full_flag;
|
|
integer i;
|
|
|
|
tri0 aclr;
|
|
tri0 sclr;
|
|
|
|
buf (i_aclr, aclr);
|
|
buf (i_sclr, sclr);
|
|
|
|
initial
|
|
begin
|
|
|
|
if (lpm_width <= 0)
|
|
$display("Error! lpm_width must be greater than 0.");
|
|
|
|
if (lpm_numwords <= 1)
|
|
$display("Error! lpm_numwords must be greater than or equal to 2.");
|
|
|
|
// check for number of words out of bound
|
|
if ((lpm_widthu !=1) && (lpm_numwords > (1 << lpm_widthu)))
|
|
$display("Error! lpm_numwords MUST equal to the ceiling of log2(lpm_widthu).");
|
|
|
|
if (lpm_numwords <= (1 << (lpm_widthu-1)))
|
|
begin
|
|
$display("Error! lpm_widthu is too big for the specified lpm_numwords.");
|
|
end
|
|
|
|
for (i=0; i < lpm_width; i=i+1)
|
|
ZEROS[i] = 1'b0;
|
|
|
|
for (i = 0; i < lpm_numwords; i=i+1)
|
|
mem_data[i] = ZEROS;
|
|
|
|
full_flag = 0;
|
|
empty_flag = 1;
|
|
read_id = 0;
|
|
write_id = 0;
|
|
count_id = 0;
|
|
tmp_q = ZEROS;
|
|
end
|
|
|
|
always @(posedge clock or i_aclr)
|
|
begin
|
|
if (i_aclr)
|
|
begin
|
|
tmp_q = ZEROS;
|
|
full_flag = 0;
|
|
empty_flag = 1;
|
|
read_id = 0;
|
|
write_id = 0;
|
|
count_id = 0;
|
|
if (lpm_showahead == "ON")
|
|
tmp_q = mem_data[0];
|
|
end
|
|
else if (clock)
|
|
begin
|
|
if (i_sclr)
|
|
begin
|
|
tmp_q = mem_data[read_id];
|
|
full_flag = 0;
|
|
empty_flag = 1;
|
|
read_id = 0;
|
|
write_id = 0;
|
|
count_id = 0;
|
|
if (lpm_showahead == "ON")
|
|
tmp_q = mem_data[0];
|
|
end
|
|
else
|
|
begin
|
|
// both WRITE and READ
|
|
if ((wrreq && !full_flag) && (rdreq && !empty_flag))
|
|
begin
|
|
mem_data[write_id] = data;
|
|
if (write_id >= lpm_numwords-1)
|
|
write_id = 0;
|
|
else
|
|
write_id = write_id + 1;
|
|
|
|
tmp_q = mem_data[read_id];
|
|
if (read_id >= lpm_numwords-1)
|
|
read_id = 0;
|
|
else
|
|
read_id = read_id + 1;
|
|
if (lpm_showahead == "ON")
|
|
tmp_q = mem_data[read_id];
|
|
end
|
|
|
|
// WRITE
|
|
else if (wrreq && !full_flag)
|
|
begin
|
|
mem_data[write_id] = data;
|
|
if (lpm_showahead == "ON")
|
|
tmp_q = mem_data[read_id];
|
|
count_id = count_id + 1;
|
|
empty_flag = 0;
|
|
if (count_id >= lpm_numwords)
|
|
begin
|
|
full_flag = 1;
|
|
count_id = lpm_numwords;
|
|
end
|
|
if (write_id >= lpm_numwords-1)
|
|
write_id = 0;
|
|
else
|
|
write_id = write_id + 1;
|
|
end
|
|
|
|
// READ
|
|
else if (rdreq && !empty_flag)
|
|
begin
|
|
tmp_q = mem_data[read_id];
|
|
count_id = count_id - 1;
|
|
full_flag = 0;
|
|
if (count_id <= 0)
|
|
begin
|
|
empty_flag = 1;
|
|
count_id = 0;
|
|
end
|
|
if (read_id >= lpm_numwords-1)
|
|
read_id = 0;
|
|
else
|
|
read_id = read_id + 1;
|
|
if (lpm_showahead == "ON")
|
|
tmp_q = mem_data[read_id];
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
assign q = tmp_q;
|
|
assign full = full_flag;
|
|
assign empty = empty_flag;
|
|
assign usedw = count_id;
|
|
|
|
// Check for previous Parameter declaration order
|
|
initial if ((lpm_width === "lpm_fifo") || (lpm_type !== "lpm_fifo"))
|
|
begin
|
|
$display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
|
|
$finish;
|
|
end
|
|
endmodule // lpm_fifo
|
|
|
|
//------------------------------------------------------------------------
|
|
|
|
module lpm_fifo_dc ( data, rdclock, wrclock, aclr, rdreq, wrreq, rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q );
|
|
|
|
// NOTE: Parameters must be declared in the same order as the Properties
|
|
// are specified in the Cell Specification document.
|
|
parameter lpm_width = 1;
|
|
parameter lpm_widthu = 1;
|
|
parameter lpm_numwords = 2;
|
|
parameter lpm_showahead = "OFF";
|
|
parameter lpm_type = "lpm_fifo_dc";
|
|
parameter lpm_hint = "UNUSED";
|
|
parameter lpm_source_version = "lpm 220 version 1.6";
|
|
|
|
input [lpm_width-1:0] data;
|
|
input rdclock;
|
|
input wrclock;
|
|
input wrreq;
|
|
input rdreq;
|
|
input aclr;
|
|
output rdfull;
|
|
output wrfull;
|
|
output rdempty;
|
|
output wrempty;
|
|
output [lpm_width-1:0] q;
|
|
output [lpm_widthu-1:0] rdusedw;
|
|
output [lpm_widthu-1:0] wrusedw;
|
|
|
|
|
|
// internal reg
|
|
reg [lpm_width-1:0] mem_data [lpm_numwords-1:0];
|
|
integer pipe_wrptr [0:5]; // [0:RDPTR_DP];
|
|
integer pipe_rdptr [0:5]; // [0:WRPTR_DP];
|
|
integer pipe_rdusedw [0:1]; // [0:RDUSEDW_DP];
|
|
integer pipe_wrusedw [0:1]; // [0:WRUSEDW_DP];
|
|
|
|
reg [lpm_width-1:0] i_q;
|
|
reg i_rdempty;
|
|
reg i_wrempty;
|
|
reg i_rdfull;
|
|
reg i_wrfull;
|
|
reg x_rdempty;
|
|
reg x_wrfull;
|
|
integer i_rdptr;
|
|
integer i_wrptr;
|
|
integer i_rdusedw;
|
|
integer i_wrusedw;
|
|
integer x_rdptr;
|
|
integer x_wrptr;
|
|
|
|
reg [lpm_width-1:0] ZEROS;
|
|
integer RDPTR_DP;
|
|
integer WRPTR_DP;
|
|
integer RDUSEDW_DP;
|
|
integer WRUSEDW_DP;
|
|
integer FULL_RISEEARLY;
|
|
integer i;
|
|
|
|
tri0 aclr;
|
|
buf (i_aclr, aclr);
|
|
|
|
|
|
initial
|
|
begin
|
|
|
|
if (lpm_width <= 0)
|
|
$display("Error! lpm_width must be greater than 0.");
|
|
|
|
if (lpm_numwords <= 1)
|
|
$display("Error! lpm_numwords must be greater than or equal to 2.");
|
|
|
|
// check for number of words out of bound
|
|
if ((lpm_widthu !=1) && (lpm_numwords > (1 << lpm_widthu)))
|
|
$display("Error! lpm_numwords MUST equal to the ceiling of log2(lpm_widthu).");
|
|
|
|
if (lpm_numwords <= (1 << (lpm_widthu-1)))
|
|
$display("Error! lpm_widthu is too big for the specified lpm_numwords.");
|
|
|
|
for (i=0; i<lpm_width; i=i+1)
|
|
ZEROS[i] = 1'b0;
|
|
|
|
// MEMORY INITIALIZATION
|
|
for (i=0; i<lpm_numwords; i=i+1)
|
|
mem_data[i] = ZEROS;
|
|
|
|
// INITERNAL VARIABLES INIT
|
|
i_q = ZEROS;
|
|
i_rdptr = 0;
|
|
i_wrptr = 0;
|
|
i_rdempty = 1;
|
|
i_wrempty = 1;
|
|
i_rdfull = 0;
|
|
i_wrfull = 0;
|
|
i_rdusedw = 0;
|
|
i_wrusedw = 0;
|
|
|
|
// CONSTANTS
|
|
RDPTR_DP = 5;
|
|
WRPTR_DP = 5;
|
|
RDUSEDW_DP = 1;
|
|
WRUSEDW_DP = 1;
|
|
FULL_RISEEARLY = 2;
|
|
|
|
// CLEAR PIPELINES
|
|
for (i=0; i<RDPTR_DP; i=i+1)
|
|
pipe_wrptr[i] = 0;
|
|
for (i=0; i<WRPTR_DP; i=i+1)
|
|
pipe_rdptr[i] = 0;
|
|
for (i=0; i<RDUSEDW_DP; i=i+1)
|
|
pipe_rdusedw[i] = 0;
|
|
for (i=0; i<WRUSEDW_DP; i=i+1)
|
|
pipe_wrusedw[i] = 0;
|
|
|
|
end
|
|
|
|
always @(i_aclr)
|
|
begin
|
|
if (i_aclr)
|
|
begin
|
|
i_q = ZEROS;
|
|
i_rdptr = 0;
|
|
i_wrptr = 0;
|
|
i_rdempty = 1;
|
|
i_wrempty = 1;
|
|
i_rdfull = 0;
|
|
i_wrfull = 0;
|
|
if (lpm_showahead == "ON")
|
|
i_q = mem_data[0];
|
|
|
|
// CLEAR PIPELINES
|
|
for (i=0; i<RDPTR_DP; i=i+1)
|
|
pipe_wrptr[i] = 0;
|
|
for (i=0; i<WRPTR_DP; i=i+1)
|
|
pipe_rdptr[i] = 0;
|
|
for (i=0; i<RDUSEDW_DP; i=i+1)
|
|
pipe_rdusedw[i] = 0;
|
|
for (i=0; i<WRUSEDW_DP; i=i+1)
|
|
pipe_wrusedw[i] = 0;
|
|
end
|
|
end
|
|
|
|
always @(posedge wrclock)
|
|
begin
|
|
if (!i_aclr)
|
|
begin
|
|
// SET FLAGS
|
|
x_wrfull = i_wrfull;
|
|
if (i_wrusedw >= lpm_numwords-1-FULL_RISEEARLY)
|
|
i_wrfull = 1;
|
|
else
|
|
i_wrfull = 0;
|
|
|
|
if ((i_wrusedw <= 0) && (i_rdptr == i_wrptr))
|
|
i_wrempty = 1;
|
|
|
|
x_wrptr = i_wrptr;
|
|
if (wrreq && !x_wrfull) // && ! wrreq'event
|
|
begin
|
|
// WRITE DATA
|
|
mem_data[i_wrptr] = data;
|
|
|
|
// SET FLAGS
|
|
i_wrempty = 0;
|
|
|
|
// INC WRPTR
|
|
if (i_wrptr >= lpm_numwords-1)
|
|
i_wrptr = 0;
|
|
else
|
|
i_wrptr = i_wrptr + 1;
|
|
end
|
|
|
|
// DELAY RDPTR FOR WRUSEDW
|
|
pipe_rdptr[WRPTR_DP] = i_rdptr;
|
|
for (i=0; i<WRPTR_DP; i=i+1)
|
|
pipe_rdptr[i] = pipe_rdptr[i+1];
|
|
if (x_wrptr >= pipe_rdptr[0])
|
|
pipe_wrusedw[WRUSEDW_DP] = x_wrptr - pipe_rdptr[0];
|
|
else
|
|
pipe_wrusedw[WRUSEDW_DP] = lpm_numwords + x_wrptr - pipe_rdptr[0];
|
|
|
|
// DELAY WRUSEDW
|
|
for (i=0; i<WRUSEDW_DP; i=i+1)
|
|
pipe_wrusedw[i] = pipe_wrusedw[i+1];
|
|
i_wrusedw = pipe_wrusedw[0];
|
|
end
|
|
end
|
|
|
|
always @(posedge rdclock)
|
|
begin
|
|
if (!i_aclr)
|
|
begin
|
|
// SET FLAGS
|
|
x_rdempty = i_rdempty;
|
|
if (i_rdusedw >= lpm_numwords-1-FULL_RISEEARLY)
|
|
i_rdfull = 1;
|
|
else
|
|
i_rdfull = 0;
|
|
|
|
if (i_rdptr == i_wrptr)
|
|
i_rdempty = 1;
|
|
else if (i_rdempty && (i_rdusedw > 0))
|
|
i_rdempty = 0;
|
|
|
|
// Q SHOWAHEAD
|
|
if (lpm_showahead == "ON" && i_rdptr != i_wrptr)
|
|
i_q = mem_data[i_rdptr];
|
|
|
|
x_rdptr = i_rdptr;
|
|
if (rdreq && !x_rdempty) // && ! rdreq'event
|
|
begin
|
|
// READ DATA
|
|
i_q = mem_data[i_rdptr];
|
|
if (lpm_showahead == "ON")
|
|
begin
|
|
if (i_rdptr == i_wrptr)
|
|
i_q = ZEROS;
|
|
else
|
|
begin
|
|
if (i_rdptr >= lpm_numwords-1)
|
|
i_q = mem_data[0];
|
|
else
|
|
i_q = mem_data[i_rdptr+1];
|
|
end
|
|
end
|
|
|
|
// SET FLAGS
|
|
if ((i_rdptr == lpm_numwords-1 && i_wrptr == 0) ||
|
|
(i_rdptr+1 == i_wrptr))
|
|
i_rdempty = 1;
|
|
|
|
// INC RDPTR
|
|
if (i_rdptr >= lpm_numwords-1)
|
|
i_rdptr = 0;
|
|
else
|
|
i_rdptr = i_rdptr + 1;
|
|
|
|
end
|
|
// DELAY WRPTR FOR RDUSEDW
|
|
pipe_wrptr[RDPTR_DP] = i_wrptr;
|
|
for (i=0; i<RDPTR_DP; i=i+1)
|
|
pipe_wrptr[i] = pipe_wrptr[i+1];
|
|
if (pipe_wrptr[0] >= x_rdptr)
|
|
pipe_rdusedw[RDUSEDW_DP] = pipe_wrptr[0] - x_rdptr;
|
|
else
|
|
pipe_rdusedw[RDUSEDW_DP] = lpm_numwords + pipe_wrptr[0] - x_rdptr;
|
|
|
|
// DELAY RDUSEDW
|
|
for (i=0; i<RDUSEDW_DP; i=i+1)
|
|
pipe_rdusedw[i] = pipe_rdusedw[i+1];
|
|
i_rdusedw = pipe_rdusedw[0];
|
|
end
|
|
end
|
|
|
|
assign q = i_q;
|
|
assign wrfull = i_wrfull;
|
|
assign wrempty = i_wrempty;
|
|
assign rdfull = i_rdfull;
|
|
assign rdempty = i_rdempty;
|
|
assign wrusedw = i_wrusedw;
|
|
assign rdusedw = i_rdusedw;
|
|
|
|
// Check for previous Parameter declaration order
|
|
initial if ((lpm_width === "lpm_fifo_dc") || (lpm_type !== "lpm_fifo_dc"))
|
|
begin
|
|
$display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation");
|
|
$finish;
|
|
end
|
|
endmodule // lpm_fifo_dc
|
|
|
No newline at end of file
|
No newline at end of file
|
