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//////////////////////////////////////////////////////////////////////
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//// ////
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//// sram_for_debugging_async #(NUM_ADDR_BITS, NUM_DATA_BITS) ////
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//// ////
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//// This file is part of the general opencores effort. ////
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//// <http://www.opencores.org/cores/misc/> ////
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//// ////
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//// Module Description: ////
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//// An SRAM model which contains only 32 entries. ////
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//// This SRAM trades off time for storage. By only storing ////
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//// a very few entries, this SRAM takes constant storage ////
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//// independent of how many address lines it exports. ////
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//// The limited storage means that the entries must be read ////
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//// soon after it is written. If too many writes happen ////
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//// before an entry is read, the entry returns X's. ////
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//// This SRAM has 1 other debugging feature. When a write ////
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//// is executed, the SRAM ;atches the bit number of the ////
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//// least significant bit of the address which is HIGH. ////
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//// The special address 0xAA00..., with the top 8 bits being ////
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//// 8'b1010_1010, returns the stored number when read. ////
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//// As an example, assume that a write is done to location ////
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//// 20'h0_0040. ////
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//// After the write, but before any other write, the user ////
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//// can read location 20'hC_C000. The read returns 4'h5. ////
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//// ////
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//// Author(s): ////
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//// - Anonymous ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Anonymous and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// $Id: sram_for_debugging_async.v,v 1.2 2001-11-06 12:33:15 bbeaver Exp $
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/10/02 05:23:27 Blue Beaver
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// no message
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//
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// Revision 1.3 2001/09/27 08:05:43 Blue Beaver
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// no message
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//
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// Revision 1.2 2001/09/26 09:46:20 Blue Beaver
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// no message
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//
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// Revision 1.1 2001/09/25 10:49:34 Blue Beaver
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// no message
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//
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`timescale 1ns/1ps
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// instantiate as "sram_for_debugging_async #(NUM_ADDR_BITS, NUM_DATA_BITS) instance ()"
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module sram_for_debugging_async (
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data_out,
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data_in,
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address,
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read_enable,
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write_enable
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);
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parameter NUM_ADDR_BITS = 1;
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parameter NUM_DATA_BITS = 1;
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output [NUM_DATA_BITS - 1 : 0] data_out;
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input [NUM_DATA_BITS - 1 : 0] data_in;
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input [NUM_ADDR_BITS - 1 : 0] address;
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input read_enable;
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input write_enable;
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reg [NUM_DATA_BITS - 1 : 0] data_storage [31:0]; // 32 entries of SRAM storage
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reg [NUM_ADDR_BITS - 1 : 0] address_storage [31:0]; // 32 entries of SRAM storage
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reg [5:0] write_counter; // enough to count to 63
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reg [NUM_DATA_BITS - 1 : 0] stored_write_address; // store bit number of address LSB set to 1
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integer i, j, k, l;
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// synopsys translate_off
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initial
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begin
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for (i = 6'h00; i != 6'h20; i = i + 6'h01)
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begin
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address_storage[i] = {NUM_ADDR_BITS{1'bX}};
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data_storage[i] = {NUM_DATA_BITS{1'bX}};
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stored_write_address[NUM_DATA_BITS - 1 : 0] = {NUM_DATA_BITS{1'bX}};
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write_counter[5:0] = 6'h00;
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end
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end
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// synopsys translate_on
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// Write to next address, remember which LSB write address bit was ~0
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always @(posedge write_enable)
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begin
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address_storage[write_counter[4:0]] = address[NUM_ADDR_BITS - 1 : 0];
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data_storage[write_counter[4:0]] = data_in[NUM_DATA_BITS - 1 : 0];
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for (j = 0; j < NUM_ADDR_BITS; j = j + 1)
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begin
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if (((address[NUM_ADDR_BITS - 1 : 0] >> j) & 1'b1) != 1'b0)
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begin
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stored_write_address[NUM_DATA_BITS - 1 : 0] = j;
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j = NUM_ADDR_BITS + 1; // only remember the FIRST bit set
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end
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end
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if (j == NUM_ADDR_BITS) // NO bit was set
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begin
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stored_write_address[NUM_DATA_BITS - 1 : 0] = NUM_ADDR_BITS;
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end
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write_counter[5:0] = (write_counter[5:0] + 6'h01) & 6'h1F;
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end
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// Starting at the newest, search back to oldest to find if the word has been written
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reg [NUM_DATA_BITS - 1 : 0] data_out;
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reg [4:0] read_address;
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always @(read_enable)
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begin
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if ((read_enable !== 1'b1) | ((^address[NUM_DATA_BITS - 1 : 0]) === 1'bX)) // no read, return X's
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begin
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data_out[NUM_DATA_BITS - 1 : 0] = {NUM_DATA_BITS{1'bX}};
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end
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else
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begin
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if ((address[NUM_ADDR_BITS - 1 : 0] >> (NUM_ADDR_BITS - 8)) == 8'hAA) // read magic location, return Address Bit Number
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begin
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data_out[NUM_DATA_BITS - 1 : 0] = stored_write_address[NUM_DATA_BITS - 1 : 0];
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end
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else // otherwise search history to see if the word has been written recently
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begin
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k = write_counter[5:0];
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for (l = k + 6'h1F; // half way around, same as last minus 1;
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l >= k; // write address not valid
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l = l - 1)
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begin
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read_address[4:0] = l;
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if (address[NUM_ADDR_BITS - 1 : 0] === address_storage[read_address[4:0]])
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begin
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data_out[NUM_DATA_BITS - 1 : 0] = data_storage[read_address[4:0]];
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l = k - 2;
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end
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end
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if (l == (k - 1)) // didn't find it at all!
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begin
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data_out[NUM_DATA_BITS - 1 : 0] = {NUM_DATA_BITS{1'bX}};
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end
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end
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end
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end
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// synopsys translate_off
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initial
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begin
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if (NUM_ADDR_BITS < 8)
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begin
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$display ("*** Exiting because %m sram_for_debugging_async Number of Address bits %d < 8",
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NUM_ADDR_BITS);
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$finish;
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end
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if (NUM_DATA_BITS < 8)
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begin
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$display ("*** Exiting because %m sram_for_debugging_async Number of Data bits %d < 8",
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NUM_DATA_BITS);
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$finish;
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end
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end
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// synopsys translate_on
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endmodule
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`define TEST_SRAM
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`ifdef TEST_SRAM
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module test_sram;
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reg [11:0] address;
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reg [8:0] data_in;
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reg read_enable, write_enable;
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wire [8:0] data_out;
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integer i;
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initial
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begin
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read_enable = 1'b0;
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write_enable = 1'b0;
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for (i = 0; i < 12; i = i + 1)
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begin
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# 0;
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address[11:0] = (12'h001 << i);
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data_in[8:0] = i + 4;
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# 0; write_enable = 1'b1;
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# 0; write_enable = 1'b0;
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# 0;
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address[11:0] = 12'hAA0;
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# 0; read_enable = 1'b1;
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# 0;
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if (data_out[8:0] !== i)
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$display ("*** Debug SRAM read failed %x %x", i, data_out[8:0]);
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# 0; read_enable = 1'b0;
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end
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for (i = 0; i < 12; i = i + 1)
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begin
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# 0;
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address[11:0] = (12'h001 << i);
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# 0; read_enable = 1'b1;
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# 0;
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if (data_out[8:0] !== (i + 4))
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$display ("*** Debug SRAM read failed %x %x", i, data_out[8:0]);
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# 0; read_enable = 1'b0;
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end
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# 0;
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address[11:0] = 12'hXXX;
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# 0; read_enable = 1'b1;
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# 0;
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if (data_out[8:0] !== 9'hXXX)
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$display ("*** Debug SRAM read failed %x %x", i, data_out[8:0]);
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# 0; read_enable = 1'b0;
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# 0;
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address[11:0] = 12'h003;
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# 0; read_enable = 1'b1;
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# 0;
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if (data_out[8:0] !== 9'hXXX)
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$display ("*** Debug SRAM read failed %x %x", i, data_out[8:0]);
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# 0; read_enable = 1'b0;
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for (i = 0; i < 32; i = i + 1)
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begin
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# 0;
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address[11:0] = i;
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data_in[8:0] = i + 32;
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# 0; write_enable = 1'b1;
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# 0; write_enable = 1'b0;
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end
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for (i = 0; i < 32; i = i + 1)
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begin
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# 0;
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address[11:0] = i;
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# 0; read_enable = 1'b1;
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# 0;
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if (data_out[8:0] !== (i + 32))
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$display ("*** Debug SRAM read failed %x %x", i, data_out[8:0]);
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# 0; read_enable = 1'b0;
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end
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end
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sram_for_debugging_async
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#(12, // NUM_ADDR_BITS
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9 // NUM_DATA_BITS
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) test_this_one (
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.data_out (data_out[8:0]),
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.data_in (data_in[8:0]),
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.address (address[11:0]),
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.read_enable (read_enable),
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.write_enable (write_enable)
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);
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endmodule
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`endif // TEST_SRAM
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