OpenCores
URL https://opencores.org/ocsvn/configurator/configurator/trunk

Subversion Repositories configurator

[/] [configurator/] [trunk/] [test/] [versatile_mem_ctrl_defines.v] - Diff between revs 9 and 10

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 9 Rev 10
Line 1... Line 1...
//=tab Main
//=tab Main
 
 
 
//=comment Select number of WB Groups
 
 
// Number of WB groups
// Number of WB groups
//=select
//=select
//`define WB_GRPS_1 // 1
//`define WB_GRPS_1 // 1
//`define WB_GRPS_2 // 2
//`define WB_GRPS_2 // 2
`define WB_GRPS_3 // 3
`define WB_GRPS_3 // 3
Line 67... Line 69...
    `define WB_GRPS_7
    `define WB_GRPS_7
    `define NR_OF_WB_GRPS 8
    `define NR_OF_WB_GRPS 8
    `define NR_OF_PORTS 8
    `define NR_OF_PORTS 8
`endif
`endif
 
 
 
//=comment Clock domain settings
 
 
// Clock domain crossing WB1
// Clock domain crossing WB1
//=select
//=select
//`define WB1_MEM_CLK // mem clk domain
//`define WB1_MEM_CLK // mem clk domain
`define WB1_CLK // wb1 clk domain
`define WB1_CLK // wb1 clk domain
//=end
//=end
Line 108... Line 112...
//=select
//=select
//`define WB8_MEM_CLK // mem clk domain
//`define WB8_MEM_CLK // mem clk domain
`define WB8_CLK // wb8 clk domain
`define WB8_CLK // wb8 clk domain
//=end
//=end
 
 
 
//=comment Misc. settings
 
 
// Module base name
// Module base name
`define BASE versatile_mem_ctrl_
`define BASE versatile_mem_ctrl_
 
 
// Memory type
// Memory type
//=select
//=select

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.