| Line 18... |
Line 18... |
);
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);
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end entity AI;
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end entity AI;
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architecture c_to_g of AI is
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architecture c_to_g of AI is
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component bram_based_stream_buffer is
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--#(.width(48), .depth(`CONNECT6AI_SYNTH_ILS_FIFO_QUEUE_DISMANTLE_LENGTH))
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port(
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clk:in std_logic;
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reset:in std_logic;
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store_ready:in std_logic;
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flush:in std_logic;
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store_req:out std_logic;
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load_req:out std_logic;
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load_ready:in std_logic;
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indata:in std_logic_vector(47 downto 0);
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outdata:out std_logic_vector(47 downto 0)
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);
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end component bram_based_stream_buffer;
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component connect6ai_synth_tcab is
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component connect6ai_synth_tcab is
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port(
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port(
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clk: in std_logic;
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clk: in std_logic;
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reset:in std_logic;
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reset:in std_logic;
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| Line 60... |
Line 74... |
rawdataout_pico_connect6ai_synth_moveout_out_2_0: out std_logic_vector(7 downto 0);
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rawdataout_pico_connect6ai_synth_moveout_out_2_0: out std_logic_vector(7 downto 0);
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rawdataout_pico_connect6ai_synth_moveout_out_3_0: out std_logic_vector(7 downto 0);
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rawdataout_pico_connect6ai_synth_moveout_out_3_0: out std_logic_vector(7 downto 0);
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rawdataout_pico_connect6ai_synth_moveout_out_4_0: out std_logic_vector(7 downto 0);
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rawdataout_pico_connect6ai_synth_moveout_out_4_0: out std_logic_vector(7 downto 0);
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rawdataout_pico_connect6ai_synth_moveout_out_5_0: out std_logic_vector(7 downto 0);
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rawdataout_pico_connect6ai_synth_moveout_out_5_0: out std_logic_vector(7 downto 0);
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rawdataout_pico_connect6ai_synth_moveout_out_6_0: out std_logic_vector(7 downto 0);
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rawdataout_pico_connect6ai_synth_moveout_out_6_0: out std_logic_vector(7 downto 0);
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rawdataout_pico_connect6ai_synth_moveout_out_7_0: out std_logic_vector(7 downto 0)
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rawdataout_pico_connect6ai_synth_moveout_out_7_0: out std_logic_vector(7 downto 0);
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instream_queue_di_0:in std_logic_vector(47 downto 0);
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instream_queue_req_0:out std_logic;
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instream_queue_ready_0:in std_logic;
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outstream_queue_do_1:out std_logic_vector(47 downto 0);
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outstream_queue_req_1:out std_logic;
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outstream_queue_ready_1:in std_logic
|
|
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);
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);
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end component connect6ai_synth_tcab;
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end component connect6ai_synth_tcab;
|
signal out_enables:std_logic_vector(7 downto 0);
|
signal out_enables:std_logic_vector(7 downto 0);
|
signal out_enables_reg:std_logic_vector(7 downto 0);
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signal out_enables_reg:std_logic_vector(7 downto 0);
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signal AI_DATA,mAI_DATA: std_logic_vector(63 downto 0);
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signal AI_DATA,mAI_DATA: std_logic_vector(63 downto 0);
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signal ils_fifo_queue_dismantle_outdata:std_logic_vector(47 downto 0);
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signal tcab_instream_queue_req_0:std_logic;
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signal ils_fifo_queue_dismantle_store_req: std_logic;
|
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signal tcab_outstream_queue_do_1:std_logic_vector(47 downto 0);
|
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signal tcab_outstream_queue_req_1:std_logic;
|
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signal ils_fifo_queue_dismantle_load_req: std_logic;
|
begin
|
begin
|
oAI_DATA<=AI_DATA;
|
oAI_DATA<=AI_DATA;
|
inst_ai:connect6ai_synth_tcab
|
inst_ai:connect6ai_synth_tcab
|
port map(
|
port map(
|
|
|
| Line 111... |
Line 137... |
rawdataout_pico_connect6ai_synth_moveout_out_2_0=> mAI_DATA(47 downto 40),
|
rawdataout_pico_connect6ai_synth_moveout_out_2_0=> mAI_DATA(47 downto 40),
|
rawdataout_pico_connect6ai_synth_moveout_out_3_0=> mAI_DATA(39 downto 32),
|
rawdataout_pico_connect6ai_synth_moveout_out_3_0=> mAI_DATA(39 downto 32),
|
rawdataout_pico_connect6ai_synth_moveout_out_4_0=> mAI_DATA(31 downto 24),
|
rawdataout_pico_connect6ai_synth_moveout_out_4_0=> mAI_DATA(31 downto 24),
|
rawdataout_pico_connect6ai_synth_moveout_out_5_0=> mAI_DATA(23 downto 16),
|
rawdataout_pico_connect6ai_synth_moveout_out_5_0=> mAI_DATA(23 downto 16),
|
rawdataout_pico_connect6ai_synth_moveout_out_6_0=> mAI_DATA(15 downto 8),
|
rawdataout_pico_connect6ai_synth_moveout_out_6_0=> mAI_DATA(15 downto 8),
|
rawdataout_pico_connect6ai_synth_moveout_out_7_0=> mAI_DATA(7 downto 0)
|
rawdataout_pico_connect6ai_synth_moveout_out_7_0=> mAI_DATA(7 downto 0),
|
|
instream_queue_di_0=>ils_fifo_queue_dismantle_outdata(47 downto 0),
|
|
instream_queue_req_0=>tcab_instream_queue_req_0,
|
|
instream_queue_ready_0=>ils_fifo_queue_dismantle_store_req,
|
|
outstream_queue_do_1=>tcab_outstream_queue_do_1(47 downto 0),
|
|
outstream_queue_req_1=>tcab_outstream_queue_req_1,
|
|
outstream_queue_ready_1=>ils_fifo_queue_dismantle_load_req
|
);
|
);
|
|
ils_fifo_queue_dismantle:bram_based_stream_buffer
|
|
--#(.width(48), .depth(`CONNECT6AI_SYNTH_ILS_FIFO_QUEUE_DISMANTLE_LENGTH))
|
|
port map(
|
|
clk=>iCLK,
|
|
reset=>not(iRST_n),
|
|
store_ready=>tcab_instream_queue_req_0,
|
|
flush=>'0',
|
|
store_req=>ils_fifo_queue_dismantle_store_req,
|
|
load_req=>ils_fifo_queue_dismantle_load_req,
|
|
load_ready=>tcab_outstream_queue_req_1,
|
|
indata=>tcab_outstream_queue_do_1(47 downto 0),
|
|
outdata=>ils_fifo_queue_dismantle_outdata(47 downto 0));
|
|
|
process(iCLK)
|
process(iCLK)
|
begin
|
begin
|
if rising_edge(iCLK) then
|
if rising_edge(iCLK) then
|
if(iAI_start='1') then
|
if(iAI_start='1') then
|
