URL https://opencores.org/ocsvn/connect-6/connect-6/trunk

Subversion Repositories connect-6

[/] [connect-6/] [trunk/] [BUILD_SCC/] [DE2/] [quartus.tcl] - Diff between revs 4 and 8

Rev 4	Rev 8
Line 34...	Line 34...
`if [ regexp -- {assertions} ${rtl} ] {`	`if [ regexp -- {assertions} ${rtl} ] {`
`continue`	`continue`
`}`	`}`
`set_global_assignment -name VERILOG_FILE "../../../rtl/${rtl}"`	`set_global_assignment -name VERILOG_FILE "../../../rtl/${rtl}"`
`}`	`}`
	`#set_global_assignment -name VERILOG_FILE ../../../../rtl_package/simu_stubs/vsim/bram_based_stream_buffer.v`
`#DE2 files`	`#DE2 files`
`set de2files [glob -directory ../../../../DE2/ -nocomplain -tails -types f -- {*\.v}]`	`set de2files [glob -directory ../../../../DE2/ -nocomplain -tails -types f -- {*\.v}]`
`foreach mcs ${de2files} {`	`foreach mcs ${de2files} {`
`if [ regexp -- {assertions} ${mcs} ] {`	`if [ regexp -- {assertions} ${mcs} ] {`
`continue`	`continue`
Line 50...	Line 50...
`if [ regexp -- {assertions} ${mcs} ] {`	`if [ regexp -- {assertions} ${mcs} ] {`
`continue`	`continue`
`}`	`}`
`set_global_assignment -name VHDL_FILE "../../../../DE2/${mcs}"`	`set_global_assignment -name VHDL_FILE "../../../../DE2/${mcs}"`
`}`	`}`
	`set_global_assignment -name VHDL_FILE "../../../../DE2/pll/pll.vhd"`
	`set_global_assignment -name MISC_FILE "../../../../DE2/pll/pll_inst.vhd"`
	`set_global_assignment -name MISC_FILE "../../../../DE2/pll/pll.cmp"`
	`set_global_assignment -name MISC_FILE "../../../../DE2/pll/pll.ppf"`
	`set_global_assignment -name MISC_FILE "../../../../DE2/pll/pll_syn.v"`

`# run the flow`	`# run the flow`
`#execute_flow -compile`	`#execute_flow -compile`

`#load_package flow`	`#load_package flow`