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[/] [cop/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Diff between revs 7 and 10
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Rev 7 |
Rev 10 |
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Line 145... |
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// generate clock
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// generate clock
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always #20 mstr_test_clk = ~mstr_test_clk;
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always #20 mstr_test_clk = ~mstr_test_clk;
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always @(posedge mstr_test_clk)
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always @(posedge mstr_test_clk)
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vector = vector + 1;
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vector <= vector + 1;
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always @(mstr_test_clk)
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always @(mstr_test_clk)
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begin
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begin
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if (osc_div <= 7)
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if (osc_div <= 7)
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osc_div = osc_div + 1;
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osc_div <= osc_div + 1;
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else
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else
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osc_div = 0;
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osc_div <= 0;
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if (osc_div == 7)
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if (osc_div == 7)
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startup_osc = !startup_osc;
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startup_osc <= !startup_osc;
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end
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end
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assign osc_clk = startup_osc && en_osc_clk;
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assign osc_clk = startup_osc && en_osc_clk;
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// hookup wishbone master model
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// hookup wishbone master model
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