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[/] [cop/] [trunk/] [rtl/] [verilog/] [cop_regs.v] - Diff between revs 2 and 9
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Rev 9 |
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input bus_clk, // Control register bus clock
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input bus_clk, // Control register bus clock
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input async_rst_b, // Async reset signal
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input async_rst_b, // Async reset signal
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input sync_reset, // Syncronous reset signal
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input sync_reset, // Syncronous reset signal
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input cop_flag, // COP Rollover Flag
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input cop_flag, // COP Rollover Flag
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input [DWIDTH-1:0] write_bus, // Write Data Bus
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input [DWIDTH-1:0] write_bus, // Write Data Bus
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input [ 4:0] write_regs, // Write Register strobes
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input [ 4:0] write_regs // Write Register strobes
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input cnt_flag_o // Counter Rollover Flag
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);
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);
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// registers
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// registers
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reg service_cop; // Service register to reload COP Timeout Counter
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reg service_cop; // Service register to reload COP Timeout Counter
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